Stabilized delay line oscillator

Details Stabilized delay line oscillator Stabilized delay line oscillator

1977-05-05

1978-07-25

Kominski, John

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

307208, 328 55, 331135, H03B 304

Patent

active

041032519

ABSTRACT:
A device and technique for providing stability to a coherent delay line clock. A voltage controllable delay is combined with the lumped delay line of a coherent delay line clock to enable the control of the period of the clock. The voltage controllable delay is obtained by comparing the clock count during a predetermined time period against a fixed number N to obtain a difference count. The difference count is then integrated to form a bias voltage for control of the additional delay. The delay line period will then be a ratio of the predetermined period to the fixed number N, which number may be digitally modified to provide a source of variable frequency.

REFERENCES:
patent: 2835807 (1958-05-01), Lubkin
patent: 3202769 (1965-08-01), Coleman, Jr.
patent: 3337800 (1967-08-01), Halley et al.
patent: 3418498 (1968-12-01), Farley
patent: 3601636 (1971-08-01), Marsh, Jr.
patent: 3631266 (1971-12-01), Kassabgi
patent: 3793591 (1974-02-01), Trinca
patent: 3831096 (1974-08-01), Brown, Jr.
patent: 4051390 (1977-09-01), Reeves
IBM Tech. Discl. Bul., "Variable Digital Delay Line", W. E. Connors, vol. No. 4, Sep. 1965.

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