Stabilized delay circuit

Details Stabilized delay circuit Stabilized delay circuit

2001-01-31

2003-09-23

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S264000

Reexamination Certificate

active

06624679

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits, and, in particular, to a delay circuit for delaying an input signal that is practically independent from the supply voltage.
BACKGROUND OF THE INVENTION
Delay circuits are essential elements in monostable pulse generators, and are widely used in devices such as synchronous memory devices. Simple delay circuits may be obtained using a chain of capacitors and inverters, which are influenced by variations of the supply voltage and temperature.
A known architecture that solves in part these problems of precision is depicted in FIG.
1
. The depicted architecture is substantially formed by two inverters in cascade and a capacitor C. The function of the capacitor C is to increase the capacitive load of the first inverter for modulating the switching delay of the second (output) inverter.
Along the discharge path of the capacitor C there is a transistor M
1
that, depending on whether it is in a full or partial conduction state, modifies the total resistance of the discharge path, and thus the decay time of the voltage on the capacitor C. Such a transistor M
1
is kept in a conduction state by a constant reference voltage V
REF
obtained by a common band-gap circuit, for example, which is independent from the temperature.
The drawback of known delay circuits is that the delay is influenced by eventual variations of the supply voltage V
DD
. The capacitor C is charged at the voltage V
DD
and is discharged at a rate determined by the current I
SC
that flows in the transistor M
1
. The current I
SC
is constant because the transistor M
1
is biased with a constant voltage V
REF
. Thus, the discharge time is directly proportional to the supply voltage V
DD
.
The delay with which the output signal V
OUT
is produced with respect to the input signal V
INPUT
is affected by a variation of the supply voltage, regardless of the cause. In devices that use delay circuits to produce pulses of a pre-established duration, any variation of the introduced delay produces a variation of the duration of the output pulse. This is a problem that is particularly felt when the generation of pulses of a precisely pre-established and stable duration must be assured under all conditions of operation. This is the case for synchronous memory devices, for example, in which any variability of the duration of pulses would limit performance at high frequencies.
There is a clear need for a delay circuit that, differently from known delay circuits, produces an output signal V
OUT
that is delayed with respect to the input signal V
INPUT
by a time interval that is substantially independent from the supply voltage of the circuit.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is an object of the present invention to provide a delay circuit that delays an input signal by a time interval that is practically independent from variations of the supply voltage.
This and other objects, advantages and features are obtained by implementing in parallel to a regulating transistor of the discharge current of a conventional delay circuit another discharge current path that is able to sink a current directly proportional to the supply voltage.
The delay circuit may comprise a first inverter fed with the input signal, a first current terminal of which is coupled to a supply node while a transistor for regulating the delay is connected between the other current terminal of the inverter and a node at a reference voltage (ground). The regulating transistor is kept in a conduction state by a biasing voltage compensated with respect to temperature variations applied to the control terminal of the transistor. A capacitor is connected between the output of the inverter and the node at a reference voltage, and a second (output) inverter is coupled in cascade to the first inverter.
According to the present invention, the delay circuit further comprises an auxiliary current path, in parallel to the regulating transistor, which is formed by a directly biased diode connected to the current terminal of the inverter and by at least another transistor in series to the diode. The transistor is kept in a conduction state by the same biasing voltage applied to the control terminal of the regulating transistor.
The diode may be formed by a transistor of the same conductivity of the other transistor and of the regulating transistor, the control terminal of which is short-circuited to the current terminal that is connected to the current terminal of the inverter. According to a preferred embodiment of the invention the regulating transistor, the second transistor and the diode-connected transistor are n-channel MOS structures.


REFERENCES:
patent: 5027053 (1991-06-01), Ohri et al.
patent: 5559990 (1996-09-01), Cheng et al.
patent: 5594391 (1997-01-01), Yoshizawa
patent: 5596539 (1997-01-01), Passow et al.
patent: 5610543 (1997-03-01), Chang et al.
patent: 5696917 (1997-12-01), Mills et al.
patent: 5966724 (1999-10-01), Ryan
patent: 6018264 (2000-01-01), Jin
patent: 6191630 (2001-02-01), Ozawa et al.
patent: 0561370 (1993-09-01), None
patent: 0961283 (1999-12-01), None

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