Stabilized current mirror circuit

Details Stabilized current mirror circuit Stabilized current mirror circuit

1997-11-06

2000-03-07

Sterrett, Jeffrey

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323315, G05F 316

Patent

active

060345187

ABSTRACT:
A stabilized current mirror circuit including a current mirror circuit 10 having an input-stage nMOS transistor 11 and an output-stage nMOS transistor 12, an error amplifier 30 in which an output current I3 decreases in response to the rise of an output potential V2 of the output-stage nMOS transistor 12 above a specified value, a current mirror circuit 20 having an input-stage pMOS transistor 22 through which the current I3 flows and an output-stage pMOS transistor 21 connected in series to the output-stage nMOS transistor 12 and an nMOS transistor 42 connected between the output-stage pMOS transistor 21 and the output-stage nMOS transistor 12. An nMOS transistor 41 connected at a current input provides a bias voltage to the gate of the nMOS transistor 42 to enable the nMOS transistor 42 to function as a norator.

REFERENCES:
patent: 4398160 (1983-08-01), Neidorff
patent: 4814724 (1989-03-01), Tanigawa
patent: 5164658 (1992-11-01), Kuwahara
patent: 5633612 (1997-05-01), Lee
patent: 5801523 (1998-09-01), Bynum
Wilson; "Recent Developments In Current Conveyors And Current-Mode Circuits"; IEEE Proceedings, vol. 137, No. 21 Apr. 1990, pp. 63-77.

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