Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-03-01
2003-05-20
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S760000
Reexamination Certificate
active
06566757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic structures and fabrication methods, and more particularly to the formation of interconnect insulation having low dielectric constants.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide.
A consequence of having of patterned conductive material separated by an insulating material, whether the conductive material is on a single level or multiple levels, is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, power dissipation, and capacitively coupled signals, also known as cross-talk.
One way to reduce the unwanted capacitance between the interconnects is to increase the distance between them. Increased spacing between interconnect has adverse consequences such as increased area requirements, and corresponding increases in manufacturing costs. Another way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant.
What is needed is a structure providing low parasitic capacitance between patterned conductors, and methods of making such a structure.
SUMMARY OF THE INVENTION
Briefly, an interconnect structure for microelectronic devices includes interconnect lines having dielectric material disposed therebetween as an intralayer dielectric and an encapsulation structure, also disposed between the interconnect lines, that reduces outgassing from the dielectric material.
In one particular embodiment of the present invention, the dielectric material is an amorphous fluorinated carbon, and the encapsulation structure includes a moisture resistant capping layer that is formed in situ.
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Endo, K, “Fluorinated Amorphous Carbon as a Low-Dielectric-Constant Interlayer Dielectric”, MRS Bulletin/ Oct. 1997, pp. 55-58.
Banerjee Indrajit
Harker Marnie L.
Wong Lawrence D.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Cuong Quang
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