Stabilization circuits and techniques for storage and retrieval

Static information storage and retrieval – Floating gate – Particular biasing

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36518503, 36518519, G11C 700

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059010894

ABSTRACT:
An integrated circuit memory system having memory cells capable of storing multiple bits per memory cell is described. The memory system has a restoring operation in which a memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge within the predetermined levels. The memory system also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erased memory cells for increasing the spread, and safety margins, between the predetermined levels.

REFERENCES:
patent: 4890259 (1989-12-01), Simko
patent: 4989179 (1991-01-01), Simko
patent: 5043940 (1991-08-01), Harari
patent: 5172338 (1992-12-01), Mehrotra
patent: 5218569 (1993-06-01), Banks
patent: 5258759 (1993-11-01), Cauwenberghs et al.
patent: 5268870 (1993-12-01), Harari
patent: 5293560 (1994-03-01), Harari
patent: 5365486 (1994-11-01), Schreck
patent: 5394362 (1995-02-01), Banks
patent: 5422842 (1995-06-01), Cernea et al.
patent: 5479170 (1995-12-01), Cauwenberghs et al.
patent: 5511020 (1996-04-01), Hu et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5657332 (1997-08-01), Auclair et al.
Bauer et al., "A Mutilevel-Cell 32Mb Flash Memory," 1995 IEEE ISSCC, Feb. 16, 1995, pp. 132-133 & 351.
Atsumi et al., "A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation," IEEE J. Solid-State Circuits (1995) 29:461-469.
Shirota et al., "A new Programming Method and Cell Architecture and for Multi-Level Nand Flash Memories," The 14th Annual IEEE Nonvolatile Semiconductor Memory Workshop, Aug. 1995, pp. 2.7.
Jung et al., "A 3.3V 128Mb Multi-Level Nand Flash Memory for Mass Storage Applications," 1996 IEEE ISSCC, Feb. 8, 1996, pp. 32-33 & 412.
Ohkawa et al., "A 98mm 3.3V 64Mb Flash Memory wiht FN-NOR Type 4-level Cell, " 1996 IEEE ISSCC, Feb. 8, 1996, pp. 36-37 & 413.
Horiguchi et al., "An Experimental Large-Capacity Semiconductor File Memory using 16-Levels/Cells Storage," IEEE J. Solid-State Circuits (1988) 23:27-33.
Bergemont et al., "NOR Virtual Ground (NVG)--A New Scaling Concept for Very High Density Flash EEPROM and its Implementation in a 0.5um Process," IEDM, Dec. 3-8, 1993, pp. 15-18.
Kim et al., "A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 6 Gbit Flash Memories," IEDM, Dec. 10-13, 1995, pp. 263-266.
Yamauchi et al., "A New Cell Stucture for Sub-quarter Micron High Density Flash Memory," IEDM, Dec. 10-13, 1995, pp. 267-270.
Kirisawa et al., "A NAND Structured Cell with a New Programming Technology for Highly Reliable 5V-only Flash EEPROM," 1990 Symposium on VLSI Technology, Jun. 4-7, 1990, pp. 129-130.
Kobayashi et al., "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable Dinor Flash Memory," IEEE J. Solid-State Circuits (1994) 29:454-460.
Kato et al., "Read-Disturb Degradation Mechanism Mechanism due to Electron Trapping in the Tunnel Oxide for Low-Voltage Flash Memories," IEDM, Dec. 11-14, 1994, pp. 45-48.
Onoda et al., "A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory," IEDM, Dec. 13-16, 1992, pp. 599-602.
Baglee et al., "The Effects of Write/Erase Cycling on Data Loss in EEPROMs," IEDM, Dec. 1-4, 1985, pp. 624-626.
Peng et al., "Flash EPROM Endurance Simulation Using Physics-Based Models," IEDM, Dec. 11-14, 1994, pp. 295-298.
Verma et al., "Reliabiltiy Performance of ETOX Based Flash Memories," 1988 IEEE International Reliability Physics Symposium, Apr. 11-13, 1988, pp. 158-166.
Ong et al., "Erratic Erase in ETOX Flash Memory Array," 1993 VLSI Symposium on Technology, May 17-19, 1993, pp. 83-84.
Cappelletti et al., "Failure Mechanisms of Flash Cell in Program/Erase Cycling," IEDM, Dec. 11-14, 1994, pp. 291-294.
Naruke et al., "Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness," IEDM, Dec. 11-14, 1988, pp. 424-427.

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