Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-07-06
2002-06-18
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S292000, C330S311000
Reexamination Certificate
active
06407636
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronics, and, more particularly, to a multistage operational amplifier capable of operating at a low power supply voltage.
For an operational amplifier, a low supply voltage corresponds to a voltage of about 1.8 volts. This voltage corresponds to the voltage of two series-connected electric cells or batteries having a rated voltage of 1.5 volts in a discharged state. In the discharged state, the batteries each have a voltage of about 0.9 volts.
An amplifier capable of operating on a voltage greater than or equal to 1.8 volt thus allows the best possible use of the energy available in the devices being powered by batteries. However, the use of the amplifier is not limited to battery powered devices.
The amplifier can be applied to various types of electronic circuits and, in particular, circuits requiring a high current gain. Thus, the amplifier can be implemented in interface circuitry, power stages, adder circuits, and filters, etc. The amplifier can also be used in portable electric devices, such as headsets and mobile phones, regardless of whether these devices are battery powered.
BACKGROUND OF THE INVENTION
A basic diagram of a known type multistage operational amplifier is illustrated in FIG.
1
. The amplifier of
FIG. 1
includes an input transconductor stage marked as reference
10
. Transconductor stage
10
includes a differential input with two input terminals
12
+ and
12
−, and one current output terminal
14
. Input terminals
12
+ and
12
− respectively correspond to a non-inverting input and an inverting input. Output
14
is linked to a gain amplifier chain including in order, a first intermediate stage
20
, a second intermediate stage
30
, and an output stage
50
. The stages are connected in parallel between power supply terminals
1
and
2
.
The first and second intermediate stages and the output stage are respectively based on first, second, and third common-emitter bipolar transistors
22
,
32
, and
52
. These transistors are respectively biased by current sources
24
,
34
, and
54
. The bases and collectors of these transistors respectively form input and output terminals of the respective stages.
The base of the first bipolar transistor
22
is connected to the current output
14
of input stage
10
, and its collector is connected to the base of the second transistor
32
. Moreover, the collector of the second transistor
32
is connected to the base of the third transistor
52
of the output stage. The collector of the third transistor
52
is an amplifier output terminal, which is more precisely marked as reference
56
. Output stage
50
is linked to an external load L, indicated as a dotted line. This load, which is not part of the amplifier, is considered to have an impedance with a capacitive portion having a value of C
1
.
Also apparent in
FIG. 1
are a number of capacitors. A first capacitor
60
, having a value of CM, is connected between the input of the first stage
20
, i.e., the base of the first transistor
22
, and the amplifier output terminal
56
. A second capacitor
62
, having a value of CM
2
, is connected between the base and the collector of the first transistor
22
, i.e., between the input and the output of the first intermediate stage
20
. A third capacitor
63
, having a value of CM
3
, is connected between the base and the collector of the third transistor
52
, i.e., between the input and the output of output stage
50
.
Capacitors
60
,
62
, and
63
are frequency compensation capacitors providing the amplifier's closed loop stability. Such capacitors are usually called “Miller capacitances”. Provisions can be made for further capacitors of the same kind. In general, frequency compensation capacitors are connected between the input of a given stage and the output of the stage, or the output of a next stage in the gain amplifier chain.
The terms next and previous are used in the course of the description to qualify a gain stage. These terms refer to a definite order within the amplifier chain, i.e., from the input stage to the output stage. This order corresponds to a signal path inside the amplifier. The Miller capacitances and external capacitors connected to the amplifier control the frequency behavior thereof and that of each of its stages.
This behavior is characterized by poles. The poles correspond to frequencies at which gain slope modifications are observed in a frequency response diagram, or Bode diagram. The Bode diagram expresses the amplifier gain as a function of the frequency of a signal passing through the amplifier.
In the example of
FIG. 1
, a first pole p
1
corresponding to output stage
50
and generated by the capacitive portion of the external load L connected to the amplifier output can be defined. The expression of the first pole p
1
, the dimension of which is an angular frequency, is as follows:
P
1
=
gm
3
C
1
In this expression, C
1
is the capacitive value of load L, and gm
3
is the transconductance of the third transistor
52
, i.e., the output stage. The first pole corresponds to a frequency f
1
, such as:
f
1
=
P
1
2
π
In the same way, a second pole corresponding to the second intermediate stage
30
can be defined. This pole is an intermediate pole and corresponds to an angular frequency p
2
, the expression of which is more complex:
P
2
=
CM
CM
2
X
gm
2
CM
3
CM, CM
2
, CM
3
are the respective values of the first, second, and third capacitors, and gm
2
is the transconductance of the second transistor
32
. The second pole corresponds to a frequency of:
f
2
=
P
2
2
π
Finally, a so-called unity gain frequency related to the first capacitor
60
, having a value of CM, is defined which provides the amplifier's closed-loop stability. The expression of the amplifier's unity gain frequency, designated as f
gu
, is:
f
gu
=
gm
2
π
CM
.
In this expression, gm designates the transconductance of input stage
10
. In order to provide amplifier stability, i.e., to avoid an interference oscillation phenomena, selection of the values CM, CM
2
, and CM
3
is done so that the following equation of stability is true:
f
gu
≦k
2
f
2
≦k
1
f
1
The variables k
1
and k
2
are multiplication factors, such as k
2
>1 and k
1
>1.
The equation above translates the fact that the pole frequencies respectively introduced by the successive stages from the amplifier input to the output must be increasing and distinct. This rule, which applies to the example of
FIG. 1
, is true for an amplifier having a different number of gain stages.
The values of the multiplication factors k and k′, generally equal to 2, must be chosen to be greater than 1 to ensure that the poles will not be mixed up. A large value of these factors ensures good amplifier stability.
As specified above, the choice of Miller capacitances is dictated by the equation of stability. Capacitances are chosen in particular so that the equation of stability is true when an amplifier quiescent or rest current is passing through the gain stage transistors. This quiescent current corresponds to the current passing through the gain stage transistors when no signal is being applied at the amplifier input.
For a given stage including one or more bipolar transistors, the transconductance value is dependent on the collector current of the transistor(s). More precisely, the following is obtained for each intermediate stage:
gm
i
=
I
i
V
T
In this expression, gm
i
and I
i
respectively designate the transistor transconductance and collector current of the stage under consideration. The term V
t
is a thermal voltage defined by:
V
t
=
kT
q
where T is temperature, k the Boltzmann constant and q the electron charge. Thus, for the second intermediate stage, the collector current of which is written as IC
2
:
gm
2
=
IC
2
V
t
In the presence of an amplifier input signal, collector currents other than the quiescent currents are flowing through the transistor collectors. Thus,
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Mottola Steven J.
STMicroelectronics S.A.
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