SRAM with transparent address latch and unlatched chip enable

Details SRAM with transparent address latch and unlatched chip enable SRAM with transparent address latch and unlatched chip enable

1991-09-05

1994-09-20

LaRoche, Eugener R.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 36523003, G11C 1134

Patent

active

053495659

ABSTRACT:
A latch ram including on a single chip a memory array, an address latch and associated row and column decoders for addressing particular locations within the memory array, data I/O and associated column I/O circuitry for inputting data to and outputting data from the memory array, and microprocessor-controlled logic for controlling the input and output of such data. The device is packaged in a 28-pin DIP or SO package.

REFERENCES:
patent: 4408305 (1983-10-01), Kuo
patent: 4451745 (1984-05-01), Itoh et al.
patent: 4494222 (1985-02-01), White et al.
patent: 4566082 (1986-02-01), Anderson
patent: 4811303 (1989-03-01), Hirai
patent: 4907203 (1990-03-01), Wada et al.
patent: 4939692 (1990-07-01), Kendall
patent: 5083296 (1992-01-01), Hara et al.

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