SRAM with constant pulse width

Details SRAM with constant pulse width SRAM with constant pulse width

1983-08-31

1987-08-04

Moffitt, James W.

Static information storage and retrieval

Powering

Conservation of power

365194, G11C 700

Patent

active

046850872

ABSTRACT:
Static random access memory having an edge-triggered power up architecture. Each element of the signal path is powered up only during the period when it is expected to be active. Separate delays are provided to tailor the delay of the power-up pulses for each separate circuit component, and separate 1-shot pulse generators, with the pulse width tailored to the power-up duration required by each circuit element, are provided for each circuit element.

REFERENCES:
patent: 4231110 (1980-10-01), Stinehelfer
patent: 4339809 (1982-07-01), Stewart
patent: 4355377 (1982-10-01), Sud et al.
patent: 4405996 (1983-09-01), Stewart
patent: 4417328 (1983-11-01), Ochii
patent: 4425633 (1984-01-01), Swain
patent: 4435793 (1984-03-01), Ochii
Konishi et al., "A 64 Kb CMOS RAM", IEEE International Solid State Circuits Conference, Digest of Tech. Papers, Feb. 12, 1982, pp. 258-259, 333.
Ochii et al., "A 15 nW Standby Power 64 Kb CMOS RAM", IEEE ISSCC, Digest of Technical Papers, Feb. 12, 1982, pp. 260-261, 334.

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