SRAM with an address and data multiplexer

Details SRAM with an address and data multiplexer SRAM with an address and data multiplexer

1992-02-28

1993-09-28

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523002, 36518905, G11C 800

Patent

active

052491609

ABSTRACT:
A latch ram including on a single chip a memory array, a multiplexed address and data bus for the input of address information and the input/output of data information on the same lines, an address latch and associated row and column decoders for addressing particular locations within the memory array, data I/O and associated column I/O circuitry for inputting data to and outputting data from the memory array, and microprocessor-controlled logic for controlling the input and output of such data. The device is packaged in a 28-pin SOG or TSOP package.

REFERENCES:
patent: 4408305 (1983-10-01), Kuo
patent: 4451745 (1984-05-01), Itoh et al.
patent: 4566082 (1986-01-01), Anderson
patent: 4811303 (1989-03-01), Hirai
patent: 4907203 (1990-03-01), Wada et al.
patent: 5083296 (1992-01-01), Hara et al.

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