SRAM shutdown circuit for FPGA to conserve power when FPGA is no

Details SRAM shutdown circuit for FPGA to conserve power when FPGA is no SRAM shutdown circuit for FPGA to conserve power when FPGA is no

1998-12-23

2000-08-08

Nguyen, Tan T.

Static information storage and retrieval

Powering

Conservation of power

365154, 326 39, 326 40, G11C 700

Patent

active

061011436

ABSTRACT:
A circuit and method for FPGAs to allow a user to supply a shutdown signal at an external pin which causes internal circuitry in the FPGA to turn off pass transistors in the word lines of every SRAM cell in the FPGA thereby preventing wasted power by current drain to ground through an SRAM cell that happens to be addressed when the FPGA is not being used.

REFERENCES:
patent: 4096584 (1978-06-01), Owen, III et al.
patent: 4455627 (1984-06-01), Oritani
patent: 4918658 (1990-04-01), Shah et al.
patent: 5563839 (1996-10-01), Herdt et al.
patent: 5646902 (1997-07-01), Park
patent: 5712826 (1998-01-01), Wong et al.

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