SRAM power reduction

Details SRAM power reduction SRAM power reduction

2005-12-20

2005-12-20

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S188000, C365S230020, C365S227000

Reexamination Certificate

active

06977860

ABSTRACT:
A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS, HIGH-to-LOW, rail-to-rail voltage swing for a read mode of operation. This consumes less power for a read operation. Senseamps for finally converting low-level signals to full logic output voltage levels are located right next to output buffers and data output pads for the SRAM. The bit lines for a memory CORE are formed in lower metal layers that are closer to the core memory cells and, thus, have higher capacitance. The present invention uses lower-capacitance top layers 4–6 of a 6 metal layer scheme for the signal lines of the differential internal data bus. An optimum configuration has the capacitance of a bitline equal to the capacitance of the differential internal data bus bit-line.

REFERENCES:
patent: 6212109 (2001-04-01), Proebsting
patent: 6608772 (2003-08-01), Ooishi
patent: 6735144 (2004-05-01), Maesako et al.

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