SRAM memory requiring reduced voltage swing during write

Details SRAM memory requiring reduced voltage swing during write SRAM memory requiring reduced voltage swing during write

1994-03-31

1995-03-07

LaRoche, Eugene R.

Static information storage and retrieval

Powering

365203, 365204, 365227, G11C 1140

Patent

active

053964691

ABSTRACT:
An SRAM comprising a plurality of SRAM storage cells connected in a plurality of rows and columns. Each storage cell has four terminals. Two terminals provide power for the storage cell, and two terminals are data terminals used in reading and writing the storage cell. The data terminals are connected to first and second bit lines in the storage cell's column via coupling transistors that are controlled by word lines associated with the various rows, there being two such bit lines associated with each column. The memory includes a power system that maintains a first potential difference between the power terminals of a storage cell when the storage cell is being read and a second potential difference between the power terminals when the storage cell is being written. The absolute value of the second potential difference is less than the absolute value of the first potential difference. This arrangement reduces the swing in potential on the bit lines needed to write a storage cell.

REFERENCES:
patent: 4514831 (1985-04-01), Oritani
patent: 4712194 (1987-12-01), Yamaguchi et al.
patent: 4901284 (1990-02-01), Ochii et al.
patent: 5309401 (1994-05-01), Suzuki et al.

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