SRAM memory device having reduced size

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438199, 252903, H01L 2976, H01L 2994, H01L 31062, H01L 31113

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060305487

ABSTRACT:
A semiconductor memory device is provided that can have the memory cell size reduced and electrical imbalance eliminated. This semiconductor memory device has gate electrodes of a driver transistor and a load transistor formed of a first polysilicon layer, and a word line also serving as a gate electrode of an access transistor formed of a different layer of a second polysilicon layer. Therefore, the gate electrodes of the driver transistor and the load transistor can be overlapped with each other in a planar manner with the word line, resulting in reduction in the planar area of the memory cell. In a cell current path, a contact portion other than a bit line contact and a GND contact is not provided. Therefore, electrical imbalance in memory cells is prevented.

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Fumitomo Matsuoka et al., High-Density Full-CMOS SRAM Cell Technology with a Deep Sub-Micron Spacing between nMOS and pMOSFET, IEICE Trans. Election., vol. E77-C, No. 8, Aug. 1994, pp. 1385-1394.

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