SRAM having enhanced cell ratio

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

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257336, 257344, 257393, 257407, 257408, 257904, H01L 2972

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active

059557460

ABSTRACT:
An SRAM cell and a method of manufacturing the same are disclosed. An SRAM cell including pull down devices, access devices and pull up devices each having source and drain regions with LDD structure, the source and drain regions of the access devices having: N.sup.+ source and drain regions; N.sup.- source and drain regions formed under the N.sup.+ source and drain regions; and P.sup.- impurity regions whose predetermined portion is overlapped with the N.sup.- source and drain region.

REFERENCES:
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patent: 5047818 (1991-09-01), Tsukamoto
patent: 5324973 (1994-06-01), Sivan
patent: 5396098 (1995-03-01), Kim et al.
patent: 5629546 (1997-05-01), Wu et al.
Patent Abstracts of Japan, Publication No. 05121695 (May 18, 1993).
Hori et al., "Quarter-Micrometer SPI (Self-Aligned Pocket Implantation) MOSFET's and Its Application for Low Supply Voltage Operation," IEEE Transation on Electron Devices, vol. 42, No. 1, pp. 78-85, Jan. 1995.

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