SRAM cell having thin film transistors as loads

Details SRAM cell having thin film transistors as loads SRAM cell having thin film transistors as loads

1997-02-27

1997-11-11

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257350, 257351, 257393, 257903, H01L 27108, H01L 2701, H01L 2976, H01L 2711

Patent

active

056867360

ABSTRACT:
In a SRAM cell including two cross-coupled inverters having an input connected to a first node and an output connected to a second node, each inverter having a load TFT of a first conductivity type and a driving MOS transistor of a second conductivity type, a drain of each of the load TFT's is connected via a connection plug to the corresponding one of the first and second nodes.

REFERENCES:
patent: 5162889 (1992-11-01), Itomi
patent: 5331170 (1994-07-01), Hayashi
patent: 5373170 (1994-12-01), Pfiester et al.
patent: 5426324 (1995-06-01), Rajeevakumar
Chen et al., "Stacked CMOS SRAM Cell," IEEE Electron Device Letters, vol. EdL-4, No. 8, Aug. 1983, pp. 272-274.
"16Mbit SRAM Cell Technologies for 2.0V Operation," by Ohkubo et al., IEEE IEDM Technical Digest, pp. 481-484, 1991 no month.

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