SRAM cell having single layer polysilicon thin film transistors

Details SRAM cell having single layer polysilicon thin film transistors SRAM cell having single layer polysilicon thin film transistors

1995-12-12

1998-03-31

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 66, 257 69, 257382, 257383, 257384, 257903, H01L 2976, H01L 2994, H01L 2711

Patent

active

057341796

ABSTRACT:
A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors. This arrangement results in a TFT SRAM cell that can be implemented using simple fabrication techniques, such as single poly logic processes or ASIC processes.

REFERENCES:
patent: 5326989 (1994-07-01), Muragishi
patent: 5336914 (1994-08-01), Andoh
patent: 5468662 (1995-11-01), Havemann
patent: 5521860 (1996-05-01), Ohkubo
Yamanaka et al., "Advanced TFT SRAM Cell Technology Using a Phase-Shift Lithography", IEEE Transactions on Electron Devices, vol. 42, No. 7, Jul. 1995.

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