SRAM cell fabrication with interlevel dielectric planarization

Details SRAM cell fabrication with interlevel dielectric planarization SRAM cell fabrication with interlevel dielectric planarization

1993-12-17

1995-03-07

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437235, 437919, H01L 2170

Patent

active

053957857

ABSTRACT:
A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

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Journal Electrochem. Soc., vol. 140, No. 4, Apr. 1993, The Effect of Plasma Cure Temperature on Spin-On Glass, by Hideo Namatsu and Kazushige Minegishi, pp. 1121-1125.
Journal Electrochem. Soc., vol. 139, No. 2, Feb. 1992, Three "Low Dt" Options for Planarizing the Pre-metal Dielectric on an Advanced Double Poly BiCMOS Process, by W. Dauksher, M. Miller, and C. Tracy, pp. 532-536.
IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, Hot-Carrier Aging of the MOS Transistor in the Presence of Spin-on Glass as the Interlevel Dielectric, by N. Lifshitz and G. Smolinsky, pp. 140-142.
Journal Electrochem. Soc., vol. 139, No. 2, Feb. 1992, Polysilicon Planarization Using Spin-On Glass, by Shrinath Ramaswami and Andrew Nagy, pp. 591-599.

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