SRAM cell controlled by non-volatile memory cell

Details SRAM cell controlled by non-volatile memory cell SRAM cell controlled by non-volatile memory cell

2006-08-29

2006-08-29

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S154000, C365S189120

Reexamination Certificate

active

07099189

ABSTRACT:
First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

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“Non-volatile SRAM (General Introduction)—nvSRAM—SRAM and EEPROM within a single chip”, ZMD®, pp. 1/4-4/4, Oct. 2001.

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