Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
1999-12-20
2001-04-24
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S182000, C365S189011, C365S230010
Reexamination Certificate
active
06222753
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, generally, to an SRAM cell arrangement having a plurality of memory cells and, more specifically, to such an SRAM cell arrangement wherein each of its memory cells respectively includes 6 vertical MOS transistors such that various contacts contact a plurality of parts of the transistors simultaneously.
2. Description of the Prior Art
An SRAM cell arrangement is a memory cell arrangement with random access to stored information. In contrast to a DRAM cell arrangement wherein the information must be refreshed at regular time intervals, the information is statically stored in an SRAM sell arrangement.
What are referred to as 6T memory cells are being increasingly utilized in SRAM cell arrangements. A 6T memory cell includes four MOS transistors interconnected as a flipflop and two selection transistors. The flipflop is one of the two stable conditions. The condition of the flipflop represents a logical quantity, 0 or 1. By driving the selection transistors via a word line, the condition can be determined via two bit lines. Thus, the information can be read out and the condition can be modified and, thus, new information can be stored.
Since the memory density is increasing from memory generation to memory generation, the required area of the 6T memory cell must be reduced from generation to generation. Semiconductor International (November 1996) pages 19 and 20, presents a 6T memory cell that can be manufactured with an area of 55F
2
, whereby F is the minimum structural size that can be manufactured in the respective technology. Self-aligned contacts (i.e., contacts without utilization of aligning masks), are produced and local connections (i.e., connections that lie within the cell, are utilized.
The present invention is based on the problem of specifying an SRAM cell arrangement that includes 6T memory cells as memory cells and can be manufactured with especially high packing density. Further, a manufacturing method for such an SRAM cell arrangement should be specified.
SUMMARY OF THE INVENTION
Such problem is addressed by the present invention in an SRAM call arrangement having a plurality of memory cells wherein each memory cell includes 6 vertical MOS transistors with connections between parts of the transistors being as follows. A first source/drain region of a first transistor is connected to a first source/drain region of a second transistor and to a first voltage terminal. A second source/drain region of the first transistor is connected to a first source/drain region of a third transistor, a first source/drain region of a fifth transistor, a gate electrode of the second transistor and a gate electrode of a fourth transistor. A gate electrode of the first transistor is connected to a second source/drain region of the second transistor, a first source/drain region of the fourth transistor, a gate electrode of the third transistor and a first source/drain region of a sixth transistor. A second source/drain region of the third transistor is connected to a second source/drain region of the fourth transistor and a second voltage terminal. A second source/drain region of the fifth transistor is connected to a first bit line. A gate electrode of the fifth transistor is connected to a gate electrode of the sixth transistor and to a word line. A second source/drain region of the sixth transistor is connected to a second bit line. The third transistor and the fourth transistor are complementary to the first transistor, the second transistor, the fifth transistor and the sixth transistor. It lies within the scope of the present invention for improving various properties of the memory cell for the SRAM cell arrangement to integrate further complements such as, for example, capacitors, into the memory cell in addition to the sixth transistors of a memory cell.
In the inventive SRAM cell arrangement, the sixth transistors of each memory cell are formed as vertical transistors. The area of the memory cell thereby becomes particularly small.
The six transistors are formed at sidewalls of stripe-shaped depressions proceeding parallel to one another, which can be formed as trenches in a substrate, as a result whereof the density of the connections is increased and the area of the memory cell is reduced. The first transistor and the second transistor are arranged at a second sidewall of a first trench; the fifth transistor and the sixth transistor are to be arranged at a second sidewall of a second trench; and the third transistor and the fourth transistor are arranged of a first sidewall of the fourth trench. Third trenches filled with insulating material can, as insulating structures, insulate parts of transistors, which are complementary with one another, from one another.
It is advantageous to respectively formed gate electrodes of the six transistors as a spacer that adjoins a horizontal conductive structure arranged outside the depressions. The structure that is formed from the spacer and the horizontal, conductive structure is also referred to as strap. It enables a separate connection of the gate electrodes via an appertaining, horizontal, conductive structure to other parts of the transistors. For producing the horizontal, conductive structure before the production of the trenches, it is advantageous to generate a conductive layer. As a result, the spacer is connected in self-aligned fashion to the horizontal, conductive structure that arises from the conductive layer.
For diminishing the plurality of contacts and, thus, the area of the memory cell, it is advantageous to arrange contacts such that they partially overlap laterally with the horizontal, include conductive structures.
For increasing the density of the connections and, thus, for reducing the area of the memory cell, it is advantageous to employ a plurality of connection planes that conductive structures, bit lines and/or word lines.
So that no current flows along the sidewalls of the depressions between neighboring source/drain regions of different transistors, highly doped channel stop regions can be generated between the transistors by oblique implantation at the sidewalls of the depressions. The channel stop regions are doped with a conductivity type that is opposite the conductivity type of the neighboring source/drain regions.
For connecting neighboring source/drain regions that are located at a different height relative to an axis that proceeds perpendicular to a surface of the substrate, it is advantageous to generate highly doped diffusion regions. The diffusion regions can be generated by oblique implantation at parts of the sidewalls of the depressions. The diffusion regions are doped with the conductivity type of the neighboring source/drain regions.
When source/drain regions are generated after generating the depressions by implantation, then it is advantageous to provide the sidewalls of the depressions with spacers and to provide parts of the memory cell with a preliminary structure before the implantation in order to protect the sidewalls and the parts of the memory cell from the implantation.
It is advantageous to formed the word line as a spacer along a sidewall of one of the depressions. The first bit line and the second bit line are formed transversely relative to the word line.
For reducing the area of the memory cell, it is advantageous when the fifth gate electrode of the fifth transistor and the sixth gate electrode of the sixth transistor are parts of the word line.
It is further advantageous to arrange memory cells neighboring along the first bit line mirror-symmetrically relative to an axis that proceeds along a center line of a depression, namely such that the depression is divided by the memory cells. The area of a memory cell is diminished as a result thereof.
It is advantageous to form transistors complementary to one another at different depressions. As a result, floors of the depressions can be continuously doped by respectively one conductivity type and can be simultaneously employed as source/drain r
Bertagnolli Emmerich
Goebel Bernd
Hasler Barbara
VON Basse Paul-Werner
Willer Josef
Fears Terrell W.
Schiff Hardin & Watte
Siemens Aktiengesellschaft
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