Squelch circuit for a digital system

Telegraphy – Systems – Printing

Patent

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Details

178 695R, 179 15BF, 179 15BS, 325 31, 325 41, 325322, 3401461AB, 3401461D, 3401461E, H04B 110, H04B 320, H04J 306

Patent

active

039626466

ABSTRACT:
A digital system for receiving digital messages transmitted in a polybinary code having a squelch circuit for inhibiting operation of the system during improper operation, said squelch system including a pair of NOR gates either of which provides an inhibit signal at the output thereof upon receiving a low or zero signal at any of thirteen inputs thereto. Six of the inputs are connected to a word detector which provides a zero output whenever any one of six words, which cannot be transmitted, are received. A seventh input is activated whenever input signals exceed a predetermined level and an eighth input is activated when a carrier oscillator drops out of synchronization. One of two other inputs are activated whenever a triplet of bits including two ones of the same polarity with a zero or one between is received. One input is activated when frame pulses are missing and another input is activated when additional frame pulses are present and the final input is activated whenever bit timing pulses are missing.

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