Squared-radix discrete Fourier transform

Details Squared-radix discrete Fourier transform Squared-radix discrete Fourier transform

1987-07-20

1988-08-30

Malzahn, David H.

Boots, shoes, and leggings

G06F 15332

Patent

active

047681594

ABSTRACT:
A radix-N.sup.2 or radix-N.sup.4 discrete Fourier transform (DFT) processor having cascaded stages alternately comprising N.sup.2 -sample memories and radix-N DFT's. Data is written into and read from the memories in a sequence permitting data to be written into a memory address immediately after the previously stored data is read from the same memory address, thereby avoiding the need for double-buffered memory. In one embodiment of the invention, two radix-N.sup.2 processors are cascaded to produce a radix-N.sup.4 DFT processor with even greater memory savings.

REFERENCES:
patent: 4282579 (1981-08-01), Speiser et al.
patent: 4293921 (1981-10-01), Smith, Jr.
patent: 4602350 (1986-07-01), Gray

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