Square root extraction circuit and floating-point square root ex

Details Square root extraction circuit and floating-point square root ex Square root extraction circuit and floating-point square root ex

1997-11-05

2000-11-14

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

061483184

ABSTRACT:
A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i-1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.

REFERENCES:
patent: 4748581 (1988-05-01), DeTroye
patent: 5128891 (1992-07-01), Lynch et al.
patent: 5331586 (1994-07-01), Kitora
patent: 5430669 (1995-07-01), Chen et al.
"Computer High-speed Operation System," Kindai Kagaku sha Co., Ltd., Sep. 1, 1980, pp. 357-363, 42-43). (English Language Abstract Attached).

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