Sputter-resistant hardmask for damascene trench/via formation

Details Sputter-resistant hardmask for damascene trench/via formation Sputter-resistant hardmask for damascene trench/via formation

1999-04-22

2000-09-19

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 38, 216 88, 438723, 438734, 438743, H01L 2100

Patent

active

061211508

ABSTRACT:
The dimensional precision and accuracy of sub-micron-sized, in-laid metallization patterns, e.g., of electroplated copper or copper alloy, formed in the surface of a dielectric layer are significantly improved by utilizing a layer of a sputter-resistant mask material formed of a high atomic mass metallic element or compound thereof during reactive ion etching of the dielectric layer by a fluorine-containing plasma for forming sub-micron-dimensioned recesses therein. After filling of the recesses, planarization, as by CMP, is conducted wherein excess thickness of the metal layer is removed, together with underlying portions of the sputter-resistant mask layer.

REFERENCES:
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5968847 (1999-10-01), Ye et al.
patent: 6017821 (2000-01-01), Yang et al.

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