Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – For liquid etchant
Reexamination Certificate
2001-12-31
2003-12-09
Mills, Gregory (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
For liquid etchant
C451S541000
Reexamination Certificate
active
06660125
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to remove nodules or re-sputter residue from processed surfaces.
(2) Description of the Prior Art
Continued improvement in semiconductor device performance has led to the technical discipline of high density interconnect technology whereby multilayer structures on a substrate are fabricated to interconnect integrated circuits. To achieve the required high wiring and the high packaging density, it is frequently necessary to fabricate a multilayer structure on the substrate thereby connecting integrated circuits to one another. Device reliability and performance require that conductor features are narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick). Since conductive patterns are typically patterned using microlithography, it is important to produce patterned layers that are substantially flat and smooth with good planarity that can serve as the base for overlying layers.
If a surface that is used in a multilayer structure is not flat and smooth, many fabrication problems occur. In a multilayer structure, a flat surface is extremely important to maintain uniform processing parameters from layer to layer. A non-flat surface results in photoresist thickness variations that require pattern or layer dependent processing conditions. The layer dependent processing greatly increases the problem complexity and leads to line width variation and reduced yield. Thus, in fabricating multilayer structures, maintaining a flat surface after fabricating each layer allows uniform layer-to-layer processing.
It is not only the topographic characteristics of the participating surfaces that determine device yield and ultimately device cost. Any deviation from the desired characteristics of metal deposition and interconnect line patterning contributes undesirable yield detractors. This to the point where the performance of interconnect patterns can have an overriding impact on device performance. This applies particularly to device reliability, product yields and device performance.
The most frequently metal for the formation of interconnect lines has been aluminum, this for applications where line density is limited. Where pure aluminum is used for this purpose, aluminum tends to absorb silicon atoms from the underlying silicon substrate, these combined particles cause spiking of the aluminum surface resulting in severe problems of reliability. Pure aluminum has therefore been replaced with aluminum to which minute traces of other metals, such as silicon, have been added. This results in a reduction in the occurrence of spiking and is therefore frequently applied. This approach however only lends itself to applications where the temperature during the device fabrication does not exceed about 450 degrees C. Above this temperature the silicon that is contained in the aluminum-silicon compound separates from the compound and forms silicon residues. This separated silicon forms nodules or identifiable particles that interfere with normal device creation in an undesirable manner. These nodules for instance can collect in contact holes and, in so doing, increase the ohmic resistance of the electrical interconnects of which these contact holes are part. A nodule than is an abnormal product of epitaxial growth due to the shape of the circumferential portion and the surface grain of the semiconductor silicon substrate. The nodules cause particle defects while the device is being formed.
It is well know in the art that, during the fabrication of VLSI and ULSI semiconductor wafers, it is of critical importance to use wafers that are free of any surface Cu
+
or Cu
++
ions since the presence of these impurities has a direct and negative effect on device yield and throughput. It is therefore of extreme importance to use effective means for the control and removal of these impurities from the surface of the wafer since these impurities may, during further high temperature processing steps, diffuse into the wafer surface thereby substantially altering the chemical composition of the wafer. In addition, impurities can be classified as donor or acceptor dopants; these dopants will have an impact on the performance of subsequently produced semiconductor devices. Yet other impurities may cause surface dislocations or internal stacking misalignments or faults, further having a negative impact on semiconductor manufacturing yield and cost. It is therefore clear that an effective method must be available to thoroughly clean the surface of the semiconductor substrate from all impurities while this process of removal may have to be repeated at various intervals during the complete processing sequence.
The formation of nodules or any other irregular deposition of extraneous particles is therefore, in the interest of device performance, yield and reliability, to be avoided. Metal defects of the nodule kind will, if a processing step of sputter metal deposition follows the occurrence of nodules, further emphasize the negative impact of the created nodules. Impacted will for instance be such processing steps as plug barrier etching or the patterning of interconnect metal lines that have been created over the surface that contains nodules. It has been observed that the occurrence of nodules on underlying surfaces can contribute to a yield loss of around 10%. The formation of surface nodules has also been found to be dependent on the surface on which the nodules form, that is the underlying material that contributes to the formation of the nodules. These surfaces are typically called target surfaces. It has in this respect been found that target surfaces that contain TiN, Ti, CoTi and Al all contribute to the formation of nodules with the surface that contains TiN being a surface where nodule formation is most pronounced. Increased nodule formation leads to increased device manufacturing problems. Contributing factors to the formation of nodules are not only the chemical composition of the target surface but also the crystal orientation of the target surface and the strength and distribution of the electromagnetic field that is used in processing chambers such as a sputter deposition chamber.
The process of the invention provides a method whereby nodules can be removed in a simple manner from a target surface, the simplicity of the procedure of the invention makes this procedure readily applicable without elaborate steps of preparation or follow-up.
U.S. Pat. No. 5,976,334 (Fu et al.), U.S. Pat. No. 5,953,827 (Or et al.) and U.S. Pat. No. 5,993,916 (Zhoa et al.) show AMT sputter tools and methods.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method and procedure for the removal of metal nodules from semiconductor surfaces.
In accordance with the objectives of the invention a new method is provided for the removal of metal residue or nodules from surfaces that are target surfaces during the process of metal sputtering. A polishing bit is applied in a rotating manner to a surface on which nodules have been formed, this application removes the nodules from the target surface and prepares the surface for further processing steps.
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patent: 5681209 (1997-10-01), Naumann et al.
patent: 5953827 (1999-09-01), Or et al.
patent: 5976334 (1999-11-01), Fu et al.
patent: 5993916 (1999-11-01), Zhao et al.
Chen Ta-Bin
Kao Chung-En
Liu Kuang-Hsing
Wang Ming-Tsong
Ackerman Stephen B.
MacArthur Sylvia R.
Mills Gregory
Saile George O.
Taiwan Semiconductor Manufacturing Company
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