Spurious-emission-reducing terminal configuration for an integra

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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327545, H01L 2182

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active

059125810

ABSTRACT:
Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

REFERENCES:
patent: 4529890 (1985-07-01), Kobayashi et al.
patent: 4710771 (1987-12-01), Banno et al.
Patent Abstracts Of Japan, vol. 013, No. 330 (E-793), Jul. 25, 1989 & JP01094646 A (Fujitsu Ltd.), Apr. 13, 1989.
Patent Abstracts Of Japan vol. 013, No. 240 (E-767), Jun. 6, 1989 & JP01042462 A (Mitsubishi Electric Corp), Feb. 14, 1989.
On-Chip Decoupling Capacitor For Logic VLSI Chips, IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, New York, US.
Copy of EPO Search Report for 96113797.3, dated Jan. 23, 1997.

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