Spread spectrum type clock generating circuit

Details Spread spectrum type clock generating circuit Spread spectrum type clock generating circuit

2000-10-17

2003-05-06

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S117000, C330S00100A, C330S010000

Reexamination Certificate

active

06559698

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating circuit, particularly to a self-modulated type clock generating circuit for spreading the frequency spectrum of an output clock.
2. Description of the Related Art
A conventional clock generating circuit for generating a high-speed clock used in a microprocessor and similar circuits such as a CPU, includes a clock generating circuit that reduces electromagnetic interference (EMI) to peripheral apparatus. One example of such a circuit is a clock circuit disclosed in Japanese Patent Laid-Open No. 235862/1995. The Japanese Patent Laid-Open No. 235862/1995, as shown in
FIG. 6
, includes a clock modulation circuit
41
for controlling a divider
42
. Divider
42
is for dividing an oscillation signal of a voltage controlled oscillator
39
included in a PLL (Phase Locked Loop). The clock modulation is done using an outside reference signal from a quartz oscillation circuit
33
. By applying modulation of a low frequency to the clock, power of the clock is not concentrated on a specific single frequency but is spread to a certain constant frequency band to thereby provide an EMI reduction effect. Numeral
35
designates a reference divider for dividing the reference signal of the quartz oscillation circuit
33
and numeral
37
designates a phase frequency comparator for comparing phases of the output of the reference divider
35
and the output of the divider
42
. Numeral
38
designates a filter, numeral
41
designates a clock modulation circuit for controlling the divider
42
and numeral
40
designates a buffer for outputting the clock to outside the circuit.
Generally, a PLL circuit receives an external reference signal. The PLL circuit has a voltage controlled oscillator and dividers to divide the reference signal and the oscillation signal from voltage controlled oscillator. Both signals are set to a common frequency referred to as a comparison frequency. An error signal is generated by comparing phases and frequencies of two divided signals. The error signal constitutes a frequency correction signal supplied to the voltage controlled oscillator. The error signal is filtered using a low pass filter referred to as a loop filter before being provided to the voltage controlled oscillator for maintaining the output of the voltage controlled oscillator continuously at a predetermined frequency to generate a high speed clock. The voltage controlled oscillator must continue oscillating without further correction between successive phase frequency comparisons. The longer the period between successive phase frequency comparisons, the wider the deviation becomes from the reference. Therefore, the higher the comparison frequency, i.e., the faster the correction of the voltage controlled oscillator is carried out, the smaller the error and the smaller the correction signal. Conversely, the lower the comparison frequency, the larger the correction signal.
Further, it is known that the main cause of an instantaneous jump phenomenon of the clock frequency which is referred to as cycle-to-cycle jitter of the clock, is a remaining component of the error signal after passing through the loop filter. Therefore, in order to restrain the cycle-to-cycle jitter, it is important to increase the comparison frequency and apply correction before the error is increased.
However, according to the above-described conventional clock generating circuit, the external reference signal is used as the internal clock for operating the clock modulation circuit. In a conventional clock generating circuit for generating a highspeed clock, the frequency of the reference signal is relatively low and a number of clocks generated between successive phase frequency comparisons is small. Therefore, in order to ensure a sufficient number of clock cycles for finishing the processing by the clock modulation circuit prior to the next successive phase frequency comparison, the comparison frequency must be reduced. As a result, the error signal is increased and the cycle-to-cycle jitter is increased.
Further, there has been reported a clock generator for executing fraction division which cannot be dealt with by a divider in a PLL. Such a clock generator uses a &Dgr;&Sgr; modulator of second order or higher to generate a fixed clock having no modulation. In this case, in order for the &Dgr;&Sgr; modulator to reproduce a direct current signal having high resolution, a &Dgr;&Sgr; modulator of second order or higher having noise random performance must be used. As is well known, the &Dgr;&Sgr; modulator has a noise shaping effect and is operated at ⅙ of an operational frequency or lower to reduce noise and operated at higher than ⅙ of the operational frequency to increase noise. The higher the order of the &Dgr;&Sgr; modulator, the more increased is the noise at high frequency, i.e., the quantization noise and accordingly, by applying the noise to the PLL, the cycle-to-cycle jitter is increased.
A problem is presented by the conventional systems applying the clock modulation system to a general 2
nd
order PLL. In the 2
nd
order PLL system, a loop filter is constituted by series connection of a first capacitor and a first resistor to the ground. The first capacitor has a capacitance value of C
L
. R
L
designates a resistance value of the first resistor. It is the common practice to connect an additional capacitor having a capacitance value C
add
sufficiently smaller than the capacitance value C
L
of the first capacitor (for example, one fiftieth) in parallel with the loop filter. With the additional capacitor (value C
add
) the system approximates a 2
nd
order PLL system. Here, it is an absolute condition for guaranteeing the stability of the system that the additional capacitor be sufficiently smaller than the first capacitor. That is, the maximum value of phase margin, constituting an index of the stability of the 2
nd
order PLL, is represented as follows by a ratio of the first capacitor to the additional capacitor:
Phase margin=|tan
−1
(
X
/&ggr;)−tan
−1
(
x
)|  (1)
where &ggr;≡(C
L
/C
add
), X≡&ohgr;&tgr;
1
, &tgr;
1
≡R
L
·C
L
.
Now, consider a case in which the ratio of the first capacitor and the additional capacitor is 1. When the ratio of the first capacitor and the additional capacitor is 1, the maximum possible phase margin becomes zero and such a system cannot be stable. Further, band &ohgr;3 dB of the system that uses the additional capacitor and approximates a 2
nd
order PLL is represented by the following:
&ohgr;3 dB=&ohgr;
n
·(−(2&zgr;
2
31 1)+((2&zgr;
2
−1)
2
+1))  (2)
where &ohgr;n=(Ko·Ip/2&pgr;N C
add
), &zgr;=½&ohgr;n&tgr;
2
, notation Ko designates a gain of the voltage controlled oscillator, notation Ip designates a current value of a charge pump, notation N designates a number of divisions performed by the divider, and &tgr;
2
=R
L
·C
add
. These notations apply to the following description.
Almost all of various parameters determining Equation (2) are normally determined by a desired output clock frequency of the clock generating circuit, and C
add
and R
L
remain as adjustable parameters. Varying C
add
can change &ohgr;n and &zgr;, whereas varying R
L
can only change &zgr;. Therefore, the band &ohgr;3 dB can be adjusted by changing on via adjusting C
add
while maintaining constant &zgr; by adjusting R
L
such that everything inside of the root sign of Equation 2 is maintained constant. However, as described above, C
add
is permitted to change relative to C
L
only in a small range. Accordingly, even when the &Dgr;&Sgr; modulation method is intended to apply to the 2
nd
order PLL, a PLL band sufficient for removing high-frequency noise generated by the &Dgr;&Sgr; modulator cannot be ensured.
SUMMARY OF THE INVENTION
The present invention includes a 2
nd
order PLL having a loop filter constituted by series connection of a first capacitor a

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