Spread spectrum receiver

Details Spread spectrum receiver Spread spectrum receiver

2000-11-21

2003-08-26

Ghayour, Mohammad H. (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S343000, C375S346000

Reexamination Certificate

active

06611550

ABSTRACT:

The present invention relates to a spread spectrum receiver and to a method of recovering data bits from a spread spectrum signal.
Low cost low power spread spectrum radio systems are being developed for use in the home for interactive control and the passing of data between hardware units. One such system is termed Firefly (formerly known as HomeRF Lite) and it is proposed to operate this system in the 2.4 GHz ISM band with a 200 kbps bit rate spread to 2.2 MHz using an 11 chip pseudo-random sequence. GMSK has been proposed for the modulation scheme as this minimises the out of band side lobes of the transmitted signal.
The low power requirement implies that the hardware units should spend a considerable amount of time in a power saving sleep mode, only waking up occasionally to determine if a relevant signal is being transmitted. The faster the detection process the more the power consumption can be reduced. Coherent detectors which employ phase locked loops and delay locked loops, for carrier and code locking respectively, are at a disadvantage with respect to saving power due to the relatively long settling times of their loop filters.
A non-coherent method of decoding a spread spectrum signal may be implemented using a matched filter, however the resulting Bit Error Rate (BER) curve as a function of Signal to Noise Radio (SNR) can be expected to suffer a penalty when compared to a coherent receiver that is synchronised to the transmitters code sequence. Typically the penalty is a loss in effective SNR of the order of 3 dB.
An object of the present invention is to improve the performance of a non-synchronised matched filter when decoding CDMA bit sequences.
According to one aspect of the present invention there is provided a method of recovering data bits from a spread spectrum signal, comprising deriving a digitally sampled chip sequence from a received spread spectrum signal, filtering the digitally sampled chip sequence in a matched filter, obtaining a running average of the output from the matched filter over successive bit periods, noting, in successive bit periods, which of the matched filter output samples corresponds to the maximum value in the running average and determining the sign of the sample in a stage of the matched filter synchronised with the maximum value and assigning a data bit value in accordance with said sign.
According to a second aspect of the present invention there is provided a receiver for a spread spectrum signal, comprising means for receiving a spread spectrum signal and for producing an analogue chip sequence, means for digitising the analogue chip sequence to produce a digitally sampled chip sequence, a digital matched filter having an input for the digitally sampled chip sequence, means coupled to an output of the matched filter for obtaining a running average of the output of the matched filter over successive bit periods, means for noting which of the matched output samples corresponds to a maximum value in the running average in successive bit periods, and decision means for noting the sign of the signal in the filter stage synchronised with the maximum value and assigning a data bit value in accordance with said sign.
By means of the present invention a degree of synchronisation is achieved by computing the running average of the magnitude of the output of the matched filter over a number of bit periods so that the true peak output position can emerge from the noise.
In computing the running average, a new RMS value {circumflex over (X)}
i
n
at each sample is computed from:
{circumflex over (X)}
i
n
=&agr;*{circumflex over (X)}
i
n−1
+(1−&agr;)*X
i
n
where X
i
n
is the absolute value of the ith matched filter output sample in the n th data bit period,
{circumflex over (X)}
i
n−1
is the corresponding ith sample running average at the end of the n−1th data bit period, and
&agr; is the averaging gain and has a value 0≦&agr;≦1. Typically &agr;=0.5 for a simple average and a higher value closer to 1 for a system more resistant to the effects of noise.
The synchronisation sample for the bit period is then taken as that matched filter output sample corresponding to the maximum {circumflex over (X)}
i
n
value. The averaging gain &agr; is typically 0.5 for a simple average but a value closer to 1.0 may be chosen to effectively average the noise over a longer period thereby increasing the noise immunity.


REFERENCES:
patent: 5265121 (1993-11-01), Stewart
patent: 5416800 (1995-05-01), Frank
patent: 5426670 (1995-06-01), Leppanen et al.
patent: 5448596 (1995-09-01), Ezran et al.
patent: 5550810 (1996-08-01), Monogioudis et al.
patent: 5912919 (1999-06-01), Lomp et al.
patent: 6014407 (2000-01-01), Hunsinger et al.
patent: 0820156 (1998-01-01), None
patent: 0820156 (1998-01-01), None

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