Pulse or digital communications – Spread spectrum
Reexamination Certificate
1999-01-20
2003-07-29
Liu, Shuwang (Department: 2634)
Pulse or digital communications
Spread spectrum
C375S133000, C375S141000, C375S146000, C375S147000, C327S269000
Reexamination Certificate
active
06600771
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to electronic circuitry for parallel clock and data transmission. More particularly, the present invention relates to reducing electromagnetic interference (EMI) during such transmission.
2. Description of Related Art
As electronic and computer technology continues to evolve, communication of data among different devices, either situated nearby or at a distance, becomes increasingly important. It is also increasingly desirable to provide such data communications at very high speeds, especially in view of the large amount of data required for data communications in intensive data consuming systems using graphical or video information, multiple input-output channels, local area networks, and the like. Hence, it is now more desirable than ever to provide for high speed data communications among different chips on a circuit board, different circuit boards in a system, and different systems with each other.
A problem of increasing significance for such data communications is substantial electromagnetic interference (EMI) radiation, often exceeding acceptable levels. As the number of data lines and the rate of data driving and transmission increases, the EMI emitted increases correspondingly.
An early prior art method of reducing EMI radiation involves physical shielding. Physical shielding may reduce EMI radiation, but physical shielding may be cumbersome and costly, and may not be effective enough to sufficiently reduce EMI radiation depending on the frequencies involved.
Electromagnetic interference may have an adverse influence on the operations of electronic equipment. Thus, there are strict regulations on electromagnetic emission covering both industrial and consumer electronic equipment. Recently, there is increasing pressure to reduce EMI from such equipment.
An on-board parallel clock and data channel as shown by the example in
FIG. 1
is a primary source of EMI for some systems. In the following analysis, we assume a dual edge clocking scheme for simplicity and since it is more favorable to the EMI problem. In the far-field, each metal wire may be considered as a single point, and the EMI power radiated by the wire trace is calculated as P(f)∝I
2
(f)·f
2
, where f is the signal frequency and I(f) is the current through the wire. For example, assuming that 8 bit data wires carry an identical alternating 01 sequence with a clock of 62.5 megahertz (MHz) with rising and falling times of 1 nanosecond (ns), an EMI peak occurs at 812.5 MHz as shown in FIG.
2
(
c
). Note that only the current waveform shown in FIG.
2
(
b
) is related with EMI rather than the voltage waveform shown in FIG.
2
(
a
).
In order to reduce the peak EMI, either the power spectrum of EMI must be evenly spread over a wide frequency range or high frequency components of the current must be reduced.
One of the conventional techniques is direct-sequence spread spectrum (DSSS), where each data is exor'ed with a pseudo-random sequence and then exor'ed with the same sequence to recover data in the receiver. This spreads the data in frequency prior to transmission and “despreads” it at the receiver, as shown by the example illustrated in FIG.
3
.
However, the DSSS technique has a substantial disadvantages and problems. One disadvantage is that the DSSS technique can be applied to data signals, but not to a clock signal. This is because the clock signal must be glitch and jitter free. In the example shown in
FIG. 3
, the EMI reduction is merely to negative 19.1 dB (decibels) at 812.5 MHz, and the remaining peak arises primarily from the unspread clock line. [1 dB=10 log
10
(P
2
/P
1
), where P
1
and P
2
represent the power of two signals.] One of the problems is that the DSSS technique requires pseudo-random (PN) code generators in both transmitter and receiver for scrambling/descrambling and synchronization between transmitter and receiver.
SUMMARY OF THE INVENTION
The above described problems and disadvantages are overcome by the present invention. The present invention relates to a new spread spectrum phase modulation (SSPM) technique that is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.
REFERENCES:
patent: 5283807 (1994-02-01), Graham
patent: 5731728 (1998-03-01), Greiss
patent: 5889819 (1999-03-01), Arnett
patent: 5974464 (1999-10-01), Shin et al.
patent: 6144242 (2000-11-01), Jeong et al.
patent: 6333896 (2001-12-01), Lee
patent: 195 17 265 (1996-11-01), None
patent: 0 828 360 (1998-03-01), None
All-Digital Multi-Phase Delay Locked Loop for Internal Timing Generation in Embedded and/or High-Speed DRAMs by Kohtaroh Gotoh, Shigetoshi Wakayama, Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Yoshinori Okajima and Masao Taguchi 1977 Symposium on VLSI Circuits—Digest of Technical Papers, Jun. 12-14, 1997, pp. 107-108.
Principles of Electromagnetic Compatibility, 3rdEdition, Oct. 1986, pp. 25-34, Artech House, Inc.
Communication Systems by Simon Haykin, 3rdEdition, Date Unknown, pp. 578-611 John Willy & Sons, Inc.
Jeong Deog-Kyoon
Kim Gyudong
Moon Yongsam
Liu Shuwang
Perkins Coie LLP
Silicon Image Inc.
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