Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
2000-09-05
2004-11-09
Le, Amanda T. (Department: 2634)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S150000, C370S503000
Reexamination Certificate
active
06816543
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a spread spectrum communications apparatus composed of a transmitter and a receiver conforming to a spread spectrum communication system, and a synchronization acquisition method therein.
BACKGROUND OF THE INVENTION
Recently, since the Federal Communications Commission has released the ISM (industrial, scientific and medical) band for spread spectrum communications, products conforming to the spread spectrum communication system have been introduced in various communication appliance fields such as cordless telephones. The spread spectrum communication system features an excellent resistivity of interference and communication security. When employing this system, the FCC permits transmission at a larger output than in the conventional analog communication system. It is therefore an advantage of this system that the communication distance can be extended. On the other hand, products conforming to this system are generally based on the digital communication system, and are hence complicated and expensive as compared with the products of the conventional analog communication system. In such a background, by adding simple circuits for spreading and de-spreading to the conventional analog communications apparatus, an inexpensive spread spectrum communications apparatus is proposed. This spread spectrum communications apparatus based on the analog communication system has the following merits.
i) The frequency demodulator is higher in receiving sensitivity as compared with the demodulator of digital system, so that the communication distance can be extended.
ii) In sound transmitting system, in particular, since coding of sound is not needed, there is no delay of sound due to encoder.
An outline of a prior art of spread spectrum communications apparatus on the basis of analog communication system and its problems are explained below by referring to the drawings.
FIG. 8
is a block diagram showing a general conventional spread spectrum communications apparatus. A first communication device
1
and a second communication device
41
individually have the own transmitter and receiver, so that they can communicate with each other by wireless means. Information input into the first communication device
1
is modulated by an FM modulator
2
, and is output as a narrow-band FM modulated signal
7
which is the same as in the conventional analog communication system. This signal
7
is added, together with a spreading code
8
generated in PN code generator
6
, to a spreader
3
, and modulated, and output as a spread spectrum modulated signal
9
. This signal
9
is further converted to radio frequency in an RF transmitter
4
and then amplified to be an RF signal
10
, which is released from a transmitting antenna
5
. On the other hand, the RF signal transmitted from the first communication device
1
is received by a receiving antenna
51
of the second communication device
41
, and is amplified in an RF receiver
52
. An RF spread spectrum modulated signal
59
output from the RF receiver
52
and a de-spreading code
65
generated in a PN code generator
58
are mixed in a de-spreader
53
. At this time, async circuit
57
controls the de-spreading code
65
so as to be synchronized with the RF spread spectrum modulated signal
59
, and an original narrow-band FM modulated signal
60
is obtained as an output signal of the de-spreader
53
. This signal
60
is converted into an intermediate frequency signal
61
in an IF section
54
, and filtered, and demodulated in an FM demodulator
55
into an original information signal.
The sync circuit
57
is a kind of sliding correlator making use of the output voltage of Received Signal Strength Indicator (RSSI) of the IF section
54
, and the correlation operation is as follows. The de-spreading code
65
used in de-spreading and the spreading code
8
in spreading in the first communication device
1
are exactly the same codes and exactly same in speed. Therefore, by sequentially changing the phase of the de-spreading code
65
for the RF spread spectrum modulated signal
59
, and monitoring the output voltage
62
of the RSSI indicating the signal level after being converted and filtered into the intermediate frequency signal
61
by the IF section
54
, it is known that a maximum voltage value is obtained when the phase is completely synchronized (when the correlation value of RF spread spectrum modulated signal
59
and de-spreading code
65
are maximum). It means that de-spreading is conducted by tracing and acquiring the phase for obtaining this maximum voltage while sliding the phase of the de-spreading code
65
. In the configuration in
FIG. 8
, the output voltage
62
of RSSI is digitized by an ADC (analog-digital converter)
56
, and in order to acquire and hold on the phase for maximizing this data value, the sync circuit
57
adjusts the phase of the PN (pseudo-noise) code generator
58
by a phase control signal
64
(hereinafter, the output voltage of the ADC is called RSSI data or RSSI voltage).
The sync circuit
57
has two operation modes, that is, sync acquisition and sync hold-on. First, the sync acquisition mode determines an approximate sync position of ½ chip unit according to the following procedure (1) to (3).
(1) The de-spreading code
65
is issued from the PN code generator
58
in a proper phase for a specific time, and the RSSI data
63
and the phase of the de-spreading code
65
at this time are recorded.
(2) Shifting the phase by ½ chip, the de-spreading code
65
is output for a specific time, and when the RSSI data
63
at this time is higher than the recorded value at step (1), the recorded value is updated.
(3) The same procedure is repeated for all phases in ½ chip unit, and jumping to the phase (sync point) corresponding to the maximum value of the obtained RSSI data
63
, the sync acquisition is completed.
In the sync hold-on mode following the completion of sync acquisition, the phase is adjusted more finely (for example, ⅛ chip) from the sync point obtained in the sync acquisition mode, and the phase is held on within ±⅛ chip from the sync point.
In a block diagram of the sync circuit in
FIG. 5
, the sync circuit
57
includes a determining section
70
, and a memory
71
.
FIG. 6
is a flowchart showing the first acquisition operation of the sync circuit. In
FIG. 6
, “PHASE” is the count value showing sequential changes of the phase of the de-spreading code
65
(PHASE=1, 2, . . . , N, where N is an integer and denotes the number of times of detection of the correlation value determined by the number of chips/phase increment, that is, the number of times of sampling). Suppose the number of chips is
127
. The RSSI is the RSSI voltage
63
(see
FIG. 1
) when the count value is “PHASE”. “PEAK” is the maximum value of the detected RSSI. “PEAKPHASE” is the count value when the RSSI is maximum.
First, the determining section
70
(see
FIG. 5
) sets initially at step S
21
shown in
FIG. 6
, waits for a specific time (step S
22
), and samples the RSSI voltage every time the phase changes sequentially (step S
23
). Next, comparing if the presently sampled RSSI voltage has exceeded the hitherto maximum value or not (step S
24
), if exceeding, the RSSI is set as a new “PEAK”, and the count value at this time is set as new “PEAKPHASE” (step S
25
). Then, judging if “PHASE” has exceeded N (in this case, N is 127/(½)=254) or not (step S
26
), and if exceeding, the first acquisition operation is terminated, and if not exceeding, the phase is advanced by ½ chip (step S
27
). At step S
24
, if judged not to be RSSI>PEAK, the process jumps to step S
26
. Thus, by storing “PEAK” as the maximum value of RSSI voltage sampled so far, when all steps of first acquisition operation in
FIG. 6
are over, the maximum value of the final RSSI voltage is stored as “PEAK”. When the first acquisition operation is complete, a second acquisition is operated in a range of 8 chips before and afte
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