Split word line ternary CAM architecture

Details Split word line ternary CAM architecture Split word line ternary CAM architecture

2002-08-23

2004-12-28

Phung, Anh (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S149000

Reexamination Certificate

active

06836419

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM). More specifically, the present invention relates to a ternary CAM architecture implementing a split word line scheme and a folded bit line architecture.
BACKGROUND OF THE INVENTION
A content addressable memory (CAM) is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data being stored within a given memory location) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., random access memory (RAM), dynamic RAM (DRAM), etc.). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and reads into or gets back the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every location has a pair of status bits that keep track of whether the location is storing valid information in it or is empty and available for writing.
Once information is stored in a memory location, it is found by comparing every bit in memory with data placed in a match detection circuit. When the content stored in the CAM memory location does not match the data placed in the match detection circuit, the CAM device returns a no match indication. When the content stored in the CAM memory location matches the data placed in the match detection circuit, the CAM device returns a match indication. In addition, the CAM may return the identification of the address location in which the desired data is stored. Thus, with a CAM, the user supplies the data and gets back the address if there is a match found in memory.
Generally, CAM includes an array of CAM cells arranged in row and column lines. Each CAM cell stores one bit of digital data and includes a circuit to allow comparing the stored data with the externally provided search data. One or more bits of information in a row constitute a word. A CAM compares a search word with a row of words stored within the CAM. During a search and compare operation, an indicator associated with each stored word produces a comparison result indicating whether or not the search word matches the stored word.
The CAM structure can be made more powerful and useful by incorporating additional logic whereby a “don't care” state can be presented in addition to the “0” state and “1” state. A “don't care” state can be stored which allows certain bits of data to be skipped from search operations. The “don't care” state can be stored by having similar charges on the two storage capacitors. In addition, additional flexibility results from the ability to store the “don't care” state in the memory itself. The use of the “don't care” state means that the CAM device has “ternary” storage capabilities.
Some of the prior art CAM cells use static storage while others use a dynamic storage element. Dynamic storage elements occupy a smaller area and are therefore preferable to obtain a large memory capacity on a single integrated circuit chip. In addition, a dynamic storage cell is more efficient for ternary storage as described above.
A dynamic CAM is cell suitable for constructing relatively high-speed and large capacity CAM arrays, having binary and ternary storage capacity. Furthermore, the CAM cell also provides a relatively stable voltage level at the match line and a relatively stable capacitance at the bit lines.
A conventional CAM cell
10
is illustrated in FIG.
1
. As shown in this figure, the CAM cell
10
includes first and second storage device(s) C
1
, C
2
in the form of capacitors. Each storage device C
1
, C
2
is capable of storing a charge representing a binary ‘1’ or a ‘0’. In a binary configuration, the CAM cell
10
stores a binary bit of digital information as ‘0’ on C
1
and ‘1’ on C
2
or ‘1’ on C
1
and ‘0’ on C
2
. Furthermore, in a ternary configuration, the CAM cell
10
attains an additional “don't care” state when both storage devices C
1
, C
2
store a ‘0’. Further shown in
FIG. 1
are the first and second cell nodes N
1
, N
2
which carry signal levels corresponding to the data stored in the CAM cell
10
. The two cell nodes N
1
, N
2
are accessible for write and read operations via first and second access transistors T
1
, T
2
, respectively. The remaining two terminals of the storage device C
1
, C
2
are connected to the cell plate voltage terminal V
CP
. The source terminals of the access transistors T
1
, T
2
are connected to the nodes N
1
, N
2
whereas their drain terminals are connected to the first and second bit lines BL
1
, BL
2
. The first and second access transistors T
1
, T
2
are responsive to and have their gate terminals connected to a word line WL.
Also shown in
FIG. 1
is a comparing circuit having first and second pull-down circuits PD
1
, PD
2
. The first pull-down circuit PD
1
consists of third and fourth pull-down transistors T
3
, T
4
respectively connected in series between a match line ML and a discharge line DL. The drain terminal of the third pull-down transistor T
3
is connected to the source terminal of the fourth pull-down transistor T
4
. The third pull-down transistor T
3
is responsive to the first cell node N
1
by having its gate connected to node N
1
. The gate of the fourth pull down transistor T
4
is connected to a first search line SL
1
. Similarly, the second pull-down circuit PD
2
consists of fifth and sixth pull-down transistors T
5
, T
6
respectively connected between the match line ML and the discharge line DL. The drain terminal of the fifth pull-down transistor T
5
is connected to the source terminal of the sixth pull-down transistor T
6
. The gate terminal of the fifth pull-down transistor T
5
is connected to the second node N
2
and the gate of the sixth pull-down transistor T
6
is connected to a second search line SL
2
. The combination of the first and second pull-down circuits PD
1
, PD
2
provides a comparison between complementary data bits stored in the storage devices C
1
, C
2
and complementary search bits carried on SL
1
and SL
2
. The result of such comparison is reflected in the match line ML being discharged by the first or the second pull-down circuit PD
1
, PD
2
if there is a data mismatch (as will be further described below).
A CAM device performs three distinct operations, a write operation, read operation and search and compare operation. The conventional CAM cell
10
has two storage devices C
1
, C
2
for storing two data bits which have independent values from each other. The storage devices C
1
, C
2
are each connected to bit lines BL
1
, BL
2
through access transistors T
1
, T
2
, respectively. The bit lines BL
1
, BL
2
allow for data to be independently written to the corresponding storage devices C
1
, C
2
. The two search lines SL
1
, SL
2
connected to the pull-down circuits PD
1
, PD
2
are used for distinct search and compare operations. A search operation consists of comparing the search bits carried on the search lines SL
1
, SL
2
to data bits stored in the first and second storage devices C
1
, C
2
. The comparing circuit couples the match line ML to the discharge line DL if a mismatch occurs between the first and second search bits and the respective first and second data bits, and when the first and second data bits have complementary values.
Furthermore,
FIG. 1
discloses a CAM cell
10
with an open bit l

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