Multiplex communications – Wide area network – Packet switching
Patent
1992-10-02
1996-09-03
Lee, Thomas C.
Multiplex communications
Wide area network
Packet switching
395728, 395478, 395550, 370 856, 364230, 3642301, 3642426, 36424292, G06F 1314, G06F 1318
Patent
active
055533108
ABSTRACT:
Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.
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Culley Paul R.
Melo Maria L.
Taylor Mark
Tipley Roger E.
Compaq Computer Corporation
Kriek Rehana P.
Lee Thomas C.
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