Split polysilicon process in CMOS image integrated circuit

Details Split polysilicon process in CMOS image integrated circuit Split polysilicon process in CMOS image integrated circuit

1999-04-26

2000-08-22

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438719, 438721, 438738, H01L 2100

Patent

active

061072117

ABSTRACT:
The invention discloses a split polycilicon process for forming poly gate and polycide gate with an almost equal height in a CMOS image integrated circuit fabricated on a substrate to reduce the sheet resistance of the poly gate electrode. First, a gate oxide layer is formed on a substrate, and then a polysilicon layer and a capped dielectric layer are sequentially deposited. Next, a poly gate is patterned by using a first photoresist layer, and then the capped dielectric layer and a portion of the polycilison layer are etched. Next, the first photoresist layer is removed. Thereafter, a silicide layer is deposited. Then, a polycide gate is patterned by using a second photoresist layer, and the silicide layer and the polysilicon layer is etched. Finally, the second photoresist layer is removed.

REFERENCES:
patent: 5872059 (1999-02-01), Doan et al.
patent: 5994234 (1999-11-01), Ouchi

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