Split phase code synchronizer and demodulator

Details Split phase code synchronizer and demodulator Split phase code synchronizer and demodulator

1976-10-12

1978-05-09

Safourek, Benedict V.

Telegraphy

Systems

Line-clearing and circuit maintenance

178 88, H04L 700

Patent

active

040888320

ABSTRACT:
An improved synchronizer for recovering the clock signal in split phase encoded data. The synchronizer includes a phase locked loop (PLL) which locks in phase with the encoded data at twice the data clock frequency. The output from the PLL is divided by two in a flip flop which is triggerable to produce an output at either 0.degree. or 180.degree. relative phase. The encoded data is detected in synchronism with the output of the flip flop and the resultant is integrated over each cycle of the flip flop signal. Comparator circuitry produces an error signal if the integrated value is within predetermined limits. A counter receives the error signals and, in response to a significant number thereof, activates the flip flop to produce its alternate phase output. In this manner, the flip flop output recovers the clock signal in proper phase.
The synchronizer may be used in combination with additionally disclosed circuitry for use as a full demodulator.

REFERENCES:
patent: 3743775 (1973-07-01), Hutchinson
patent: 3820083 (1974-06-01), Way
patent: 3932705 (1976-01-01), Wolleman
patent: 3967061 (1976-06-01), Dobias
patent: 3967062 (1976-06-01), Dobias

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