Split multiplier array and method of operation

Details Split multiplier array and method of operation Split multiplier array and method of operation

2006-04-04

2006-04-04

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S625000

Reexamination Certificate

active

07024444

ABSTRACT:
There is disclosed a multiplier circuit for use in a data processor. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also comprises a split array for adding the partial products. A first summation array comprises a first group of adders that sum the even partial products to produce an even summation value. A second summation array comprises a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.

REFERENCES:
patent: 4679164 (1987-07-01), Rearick
patent: 4754421 (1988-06-01), Bosshart
patent: 6032170 (2000-02-01), Guttag et al.
patent: 6286023 (2001-09-01), Purcell et al.
patent: 6286024 (2001-09-01), Yano et al.
patent: 6370559 (2002-04-01), Hoffman

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