Split low order internal address bus for microprocessor

Details Split low order internal address bus for microprocessor Split low order internal address bus for microprocessor

1974-10-30

1976-06-08

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 300, G06F 1300

Patent

active

039626822

ABSTRACT:
A program register is coupled between a data bus N bits wide and an address but N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. for certain instructions, the address bus is be utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter depending on the type of instruction being executed. The address bus is divided into two sections, each N bits wide, one for transferring higher order address bits and the other for independently transferring lower order address bits. This architecture permits execution of many instructions in fewer machine cycles than was previously possible.

REFERENCES:
patent: 3061192 (1962-10-01), Terzian
patent: 3309679 (1967-03-01), Weisbecker
patent: 3372382 (1968-03-01), Newman
patent: 3702988 (1972-11-01), Haney
patent: 3748649 (1973-07-01), McEowen
patent: 3757306 (1973-09-01), Boone

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