Split gate NAND flash memory structure and array, method of...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185050

Reexamination Certificate

active

07808839

ABSTRACT:
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

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