Split gate memory array having staggered floating gate rows and

Details Split gate memory array having staggered floating gate rows and Split gate memory array having staggered floating gate rows and

1988-10-17

1991-06-04

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 239, 357 2311, 357 41, 357 45, 365185, H01L 2968, H01L 2702, H01L 2710

Patent

active

050218476

ABSTRACT:
An EPROM array has plural rows of split gate transistors, where each transistor includes a floating gate and the floating gate has corner portions. A bit-line defining edge is formed on each floating gate between two of the corners. The bit-line defining edges of first and second floating gates respectively belonging to first and second rows are patterned so that these edges protrude into opposed side areas of a bit line implant window. This arrangement minimizes resistance changes in the bit lines due to mask misalignment. The misalignment insensitivity permits relaxation of dimensional constraints. Cells of the memory array can be drawn to have smaller areas.

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