Split-gate flash cell for virtual ground architecture

Details Split-gate flash cell for virtual ground architecture Split-gate flash cell for virtual ground architecture

2001-05-17

2002-02-05

Lebentritt, Michael (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C365S185290

Reexamination Certificate

active

06344997

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memories and in particular split gate flash memory cells
2. Description of Related Art
Split gate flash memory technology requires a relatively large cell size compared to other type memory technologies. This is in part caused by misalignment problems and not being able to take advantage of self alignment techniques. Some designs of flash memory cells have multiple storage bits per each memory cell to accommodate the increased demand storage density, but this usually comes with an increased program current.
In U.S. Pat. No. 5,838,618 (Lee et al.) a method is disclosed to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide are eliminated to maintain separation of the programmed and erased thresholds. In U.S. Pat. No. 5,508,995 (Zimmer et al.) is described a split gate EPROM cell with buried bit lines on either side of a storage cell. The source for the EPROM cell is in part a buried bit line on one side of the storage cell and the drain is in part a buried bit line on the other side of the cell In U.S. Pat. No. 5,440,158 (Sung-Mu) is shown an EPROM cell with dual sidewall floating gates. Source and drain regions are formed between and on either side of the floating gates and a control gate is formed over the floating gates. In U.S. Pat. No. 5,067,108 (Jenq), an electrically conductive re-crystallized floating gate is disposed over an insulating area extending over a portion of a channel region and a drain region. A control gate partially overlaps the floating gate and extends over a portion of a source region.
With the demands for increased density for flash memory chips, it is important to create a small cell size that can be easy to shrink. The demand for increased density will require a solution to the misalignment problem in conventional split gate flash memories, and the minimizing of requirements for metalization and contact areas. To deal with the density requirement a cell architecture is required that has floating gates with source and drain areas that are in part a portion of buried bit lines and a control gate that extends beyond the cell to form in part a word line for the flash memory. Doing these items of improvement can produce an architecture for a split gate flash memory cell that will allow the cell to be reduced in size producing a higher flash memory density.
SUMMARY OF THE INVENTION
In this invention bit lines for a flash memory are ion implanted into a semiconductor substrate. The bit lines lay beside and extend partially under each column of floating gates and run the length of each column. A control gate is formed over each row of floating gates and runs the length of each row. The control gate of each row of floating gates serves as a word line for that row. Combinations of voltages applied to a control gate overlaying a row of floating gates and to bit lines on either side of a floating gate in that row, allow the floating gate to be programmed, read and erased. This invention is a virtual ground architecture since a bit line acts as a drain for floating gates on one side of the bit line with Vcc being applied and acts as a source for floating gates on the opposite side of the bit line with zero volts being applied.
Bit lines are alternately used as drains and sources as spit gate transistors are formed between adjacent columns. A bit line physically associated with a first column of floating gates and separated from a second column by a channel length in the semiconductor substrate is a source for the split gate transistors formed between the first and second columns of floating gates. A bit line physically associate with the second column and partially laying under the floating gates of the second column is the drain for the split gate transistors formed between the first and second columns. In like manner, the bit line physically associated with the second column and spaced by a channel length from the floating gate of a third column is a source for the split gate transistors formed between the second and third columns. The buried bit line physically associated with the third column is the drain for the split gate transistors formed between the second and third columns.
A flash memory cell comprises a floating gate with a buried bit line extending partially under the floating gate, a buried bit line from an adjacent column separated from the floating gate by a portion of a channel length, and a control gate running the length of the row containing the floating gate. The flash memory cell is programmed by applying a high voltage to the control gate, a moderate voltage to the bit line lay beside and extending partially under the floating gate, and applying zero volts to the bit line in the adjacent column. Electrons flowing from the bit line of the adjacent column gain energy as they flow through the channel between the two bit lines and are injected into the floating gate caused by impact ionization in the channel. The floating gate is erased by applying a high voltage to the surrounding bit lines and zero volts to the control gate. The erasure that removes electrons from the floating gate is done by means of Fowler-Nordheim tunneling from the floating gate and the bit line partially extending under the floating gate. The floating gate is read by applying a moderate voltage to the control gate, applying a moderate voltage of lower magnitude than that applied to the control gate to the buried bit line from the adjacent column and applying zero volts to the buried bit line partially extending under the floating gate being read.


REFERENCES:
patent: 5067108 (1991-11-01), Jeng
patent: 5278439 (1994-01-01), Ma et al.
patent: 5440158 (1995-08-01), Sung-Mu
patent: 5508955 (1996-04-01), Zimmer et al.
patent: 5670809 (1997-09-01), Saitoh
patent: 5714412 (1998-02-01), Liang et al.
patent: 5838618 (1998-11-01), Lee et al.
patent: 5986934 (1999-11-01), Kao et al.
patent: 6097059 (2000-08-01), Yamada
patent: 6204530 (2001-03-01), Choi

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