Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-03-05
2002-10-01
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C365S185230
Reexamination Certificate
active
06459616
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to Electrically Erasable Programmable Read Only Memory (EEPROM), and more particularly to an EEPROM array having a split common source for reducing Vpp loading during programming memory bit cells of the EEPROM array.
BACKGROUND OF THE INVENTION TECHNOLOGY
EEPROM is a class of nonvolatile semiconductor memory in which information may be electronically programmed into and erased from each memory element or bit cell. Each bit cell of the EEPROM comprises two metal oxide semiconductor field effect transistors (MOSFET), one of the MOSFETs has two gates and is used to store the bit information, and the other MOSFET is used in the selection of the bit cell. Illustrated in
FIG. 1
a
is a cross-section elevation view of a semiconductor integrated circuit bit cell
200
comprising a storage MOSFET
202
having two gates, a memory cell gate
102
and a floating gate
104
, one above the other. A source well
108
and common drain/source well
118
make up the remaining elements of the MOSFET
202
. A row select MOSFET
204
comprises the common drain/source well
118
, a row select gate
112
and a drain well
110
.
FIG. 1
b
is a schematic diagram of the bit cell
200
illustrated in
FIG. 1
a
. The gates
102
,
104
and
112
may be poly-silicon or other conductive material. The lower gate
104
is surrounded by an oxide
114
and is thereby insulated from and unconnected to any voltage or other element of the bit cell MOSFET
200
. The double gate MOSFET
202
is called a “floating-gate tunneling-oxide” or FLOTOX EEPROM.
FIG. 2
is a schematic diagram illustrating a portion of a typical prior art EEPROM comprising a plurality of bit cells
200
arranged in a matrix array. The memory element or bit cell generally indicated by the numeral
200
may be read from, written to, erased, or put in standby according to Table I below:
TABLE I
Read
Write
Erase
Standby
Bit Line
~1.6 volts
V
pp
0.0 volts
0.0 volts
Row Select Gate
V
DD
V
pp+
V
pp+
0.0 volts
Memory Cell Gate
~1.1 volts
0.00 volts
V
pp
0.0 volts
Common Source
0.0 volts
Float
0.0 volts
0.0 volts
V
DD
may be generally from about 5.0 volts but may be in the one volt range depending upon the operation of the EEPROM. Vpp may be generally from about 18-23 volts. Vpp+ may be generally from about 21-25 volts.
To erase or write to a bit cell
200
, the row select transistor must have a relatively high potential pulse of Vpp+. The Vpp+ pulse, and any other high potential voltages required, may be internally generated in the EEPROM integrated circuit by a charge pump, with the only other external voltage required being V
DD
. Vpp may be derived form Vpp+ and is therefore part of the load on the charge pump. The only difference between an Erase and a Write is the direction of the applied field potential relative to the floating gate
104
. The high voltage Vpp+ pulse may be from about 0.1 to 10 milliseconds.
For example, when Vpp is applied to the memory cell gate
222
b
and 0 volt is applied to bit line drain (column)
230
c
, electrons tunnel from the substrate
106
through the dielectric oxide
114
to the floating gate
104
until the floating gate
104
is charged. The cell
200
is now at an Erase state of logic 1. When 0 volt is applied to the memory cell gate
222
b
and Vpp is applied to bit line drain (column)
230
c
, electrons tunnel from the floating gate
104
through the dielectric oxide
114
to the substrate
106
until the floating gate
104
is discharged. The cell
200
is now at a Write state of logic 0. This sequence of transferring charge onto the floating gate
104
(Erase) and the removal of the charge therefrom (Write) is one Erase/Write cycle, or “E/W cycle.” Incidental to writing the bit cell
200
, the source
108
is pulled high (to approximately 10 volts).
For reliable operation of an Erase/Write cycle to a bit cell(s), the Vpp+ pulse must charge up to its maximum value quickly. A finite amount of time at finite voltages are required to achieve “optimal” Erase and Write thresholds. If the Vpp+ pulse is too short and the voltage applied to the bit cell too low, the bit cell(s)
200
will not be programmed to the proper threshold, thereby degrading the reliability and robustness of data stored in the EEPROM.
The on-chip charge pump has limited charging capabilities to generate the Vpp+ pulse during a write operation. A significant amount of capacitance and cell leakage currents load the output of the charge pump. The capacitance comprises the parallel combination of the parasitic capacitance Cgs and Cds present at each of the MOSFETs
202
and
204
in the bit cell
200
. The cell leakage is from imperfect insulation properties of materials used in fabrication of the EEPROM and elevated operating temperatures. Also, the array source
108
has a large amount of capacitance to the substrate which must be pulled high by the charge pump.
As EEPROM array bit densities increase, the on-chip charge pump of such a chip begins having trouble pulling the Vpp+ line to a reliable programming voltage during a write cycle. Attempts have been made to increase the drive (charging) capabilities of the charge pump so as to obtain the desired programming response time with a larger (higher capacitive) load. Also, attempts at reducing the Vpp+ leakage have been made to further reduce the loading of the charge pump during a write cycle. High drive capacity (stronger) charge pumps require more integrated circuit die area and/or more operating current. Reducing the bit cell device leakage currents would also require larger device structures with a resultant increase in die size. As higher bit capacity EEPROMs are being fabricated using smaller transistor structures, these attempts at improving cell writing reliability are counter productive or impossible to achieve.
SUMMARY OF THE INVENTION
The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing an EEPROM bit cell array structure having the array source lines divided into two or more segments for reducing the bit cell loading of the Vpp+ pulse during a Write operation. These segments may be as small as only the bit cells being written to (one byte, word, etc.). The charge pump need only be connected to the bit cell segment being programmed. Segmentation of the common source reduces the amount of parasitic capacitance connected in the EEPROM array during a Write operation. Reducing the number of bit cells connected during a Write operation may further reduce the amount of leakage current contributions to a bit cell(s) in a segment(s). A further reduction in charge pump drive capacitance is feasible since a reduction of loading can be achieved through appropriate segmentation of the bit cell array devices.
Accordingly, an exemplary embodiment of the invention is directed to an electrically erasable and programmable read only memory (EEPROM), comprising a plurality of memory bit cells wherein said plurality of memory bit cells are divided into at least two groups of bit cells, each of said at least two groups of bits cells have a common circuit connection separate from the other ones of said at least two groups of bits cells, and at least two selection circuits, each of said at least two selection circuits connected to the common circuit connection of a respective one of said at least two groups of bit cells, wherein said at least two selection circuits are adapted for selecting one of said at least two groups of bits cells when performing an operation on at least one bit cell thereof.
In accordance with an exemplary embodiment of the present invention, the bit cell array of an EEPROM has connections to the sources of the transistor devices comprising the bit cells segmented into two or more separate circuits. This segmentation reduces charge pump loading during a write operation to a selected bit cell(s) by reducing the number of transistor devices that contribute parasit
Beauchamp Bruce
Salt Tom
Baker & Botts L.L.P.
Hoang Huan
Microchip Technology Incorporated
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