Split bus multiprocessing system with data transfer between main

Details Split bus multiprocessing system with data transfer between main Split bus multiprocessing system with data transfer between main

1985-02-05

1990-07-10

Williams, Jr., Archie E.

Boots, shoes, and leggings

3642402, 36424343, 36424344, G06F 1316, G06F 1338, G06F 1200

Patent

active

049410881

ABSTRACT:
In a data processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus can be increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units coupled thereto. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus. The system bus is divided into a plurality of sub-bus units to handle separate functions of data transfer. The main memory unit has apparatus for efficient execution of the write-modify-read operation. In addition, the cache memory units can be divided in a plurality of sub-units and the access to the system bus arranged in terms of cyclic access of the cache memory subunits.

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patent: 4449183 (1984-05-01), Flahive
patent: 4604743 (1986-08-01), Alexandru
patent: 4695943 (1987-09-01), Keeley et al.

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