Split bus architecture for multipoint control unit

Details Split bus architecture for multipoint control unit Split bus architecture for multipoint control unit

1995-09-21

1998-05-19

Donaghue, Larry D.

39520078, 39520079, 395881, H04M 715

Patent

active

057548366

ABSTRACT:
A split bus arrangement for increasing network interface bandwidth capacity in a multipoint control unit includes a bus clock circuit for passing clock signals from a first network bus to a second network bus over a common interprocessor bus. A preferred timing arrangement provides frequency and phase lock among processor units communicating on the common interprocessor bus.

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