Split array semiconductor graphics memory architecture supportin

Details Split array semiconductor graphics memory architecture supportin Split array semiconductor graphics memory architecture supportin

1998-07-14

2000-09-19

Phan, Trong

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523002, 36518902, G11C 800, G11C 1604

Patent

active

061222194

ABSTRACT:
A semiconductor memory column decoder has first and second groups of parallel column lines (or column line pairs). The first and second groups of column lines are separated from each other by a gap. One or more groups of fractional I/O lines are provided, wherein each fractional I/O line is collinear with each other fractional I/O line of the same group. One fractional I/O line is provided for, and is connected to, each column line of the first and second groups of column lines. A plurality of multiplexers is provided, including one multiplexer corresponding to each fractional I/O line. Each multiplexer has an input connected to a single data line, a select input connected to a corresponding column select line, and an output connected to the corresponding fractional I/O line. At least some of the multiplexers are disposed in the gap.

REFERENCES:
patent: 5321665 (1994-06-01), Balistreri et al.
patent: 5579280 (1996-11-01), Son et al.
patent: 5808959 (1998-09-01), Kengeri et al.

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