Spin-on glass processing technique for the fabrication of semico

Details Spin-on glass processing technique for the fabrication of semico Spin-on glass processing technique for the fabrication of semico

1992-09-30

1994-06-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, H01L 21465

Patent

active

053209834

DESCRIPTION:

BRIEF SUMMARY
This invention relates to spin-on glass, and more particularly to a method of applying spin-on glass, especially inorganic or quasi-inorganic spin-on glass, to a semiconductor device without causing cracking or damage to the device.
Spin-on glasses (SOGs) are proprietary liquid solutions containing siloxane or silicate based monomers dissolved in various kinds of solvents or alcohols. During coating and curing, monomers are polymerized by condensation and release water, alcohol and other solvents.
The cured material is a thin solid film havingmechanical, chemical and electrical properties that depend on the starting solution, and the coating and curing process.
A primary use of SOGs is in the planarization of dielectrics in the fabrication of semi-conductor devices. As will be explained in more detail below, during the fabrication process trenches are formed in the dielectric layer. Especially at high packing densities it becomes important to fill in these trenches to provide an even surface for further processsing. This process is known as "planarization."
Among many of the dielectric planarization techniques, SOG planarization is a particularly attractive method. It is relatively simple, economical and is capable of high throughput. SOG planarization can be used over polysilicon, refractory metals, polycides, silicides, aluminum and aluminum alloys, copper, and gold, where the main goal is to-smooth or eliminate steps in the surface and enhance step coverage by the dielectrics and interconnects.
SOG planarization can take three forms:
Major manufacturing restrictions of the complete/partial etchback techniques impose the nonetchback approach as the preferred one in a production environment.
In this approach, SOG becomes a permanent part of the dielectric. Film properties are then of prime importance. Since SOG is generally a more porous material, when compared to LPCVD, APCVD, LACVD, PhACVD or PECVD oxides, it is more prone to water absorption. This water absorption reduces the bulk resistivity of the SOG and increases the power consumption of the semiconductor device due to current leakage between adjacent tracks of the same level of interconnect. For this reason, among others, SOG does not contact directly these tracks and is sandwiched between two denser LPCVD, APCVD, LACVD, PhACVD or PECVD dielectric films.
Interconnections are required between the upper and lower tracks, requiring the use of contacts or vias, and the SOG is then in direct contact with the interconnects at those locations. If too much water is present in the SOG, problems such as via poisoning can occur.
There are more than one hundred different SOG solutions on the market. These are classified in two major families:
.multidot. Quasi-inorganic SOGs
.multidot. Purely-inorganic SOGs.
Purely inorganic silicate SOGs are prone to severe cracking. The quasi-inorganic siloxane SOGs have a more flexible structure due to the presence of some organic radicals which prevent complete cross-linking of the SiO.sub.x C.sub.y H.sub.z matrix under condensation. The flexible structure reduces the tendency of an organic SOG to crack, but unfortunately the presence of the hydrogen atoms in the quasi-inorganic SOGs impairs the dielectric properties and essentially rules them out for use in sensitive CMOS devices.
Furthermore, the organic radicals are not stable at high temperatures and are not compatible with oxygen plasma photoresist strippers, which tend to transform the quasi-inorganic SOG to a purely inorganic SOG by burning the organic bonds and producing volatile compounds like H.sub.2 O, CO.sub.x H.sub.y, and silanol Si--OH. While inorganic SOGs are preferred, which are not degraded by the photoresist strippers, the cracking problem has imposed severe restrictions on layer thickness and thus the degree of planarization that can be achieved.
Planarization technology becomes increasingly important when the scale of integrated circuits shrinks to micron and sub-micron region.
Various techniques have been proposed to reduce cracking in inorganic SOG l

REFERENCES:
patent: 4185294 (1980-01-01), Sumimoto et al.
patent: 4826709 (1989-05-01), Ryan et al.
patent: 5003062 (1991-03-01), Yen
G. Smolinsky, et al. "Material Properties of Spin-on Sox for Fully Recessed NMOS Field Isolation" J. Electrochem. Soc. vol. 137(1) Jan. 1990 pp. 229-233.
K. Osinski, et al. "A 1 .mu.m CMOS Process for Logic Applications" Phillips J. Res. 44 (2,3) 1989 pp. 257-293.
M. Kuisl "Silicon Oxide Films Prepared by Spin-On Solutions" Thin Solid Films 157(1) Feb. 15, 1988 pp. 129-134.
Yen, et al. "Process Integration with Spin-on Glass . . . " 5th IEEE VLSI Conference, Jun. 13-14, 1988 pp. 85-94.
Nishida et al, "Multilevel Interconnection for 1/2.mu. VLSI's" 5th International IEEE VLSI Conf., pp. 19-25, 1988.
Forester et al., "SOG Planarization . . . " 5th International IEEE VLSI Conf. Jun. 13-14, 1988, pp. 72-79.

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