Spin-on-glass planarization process with ion implantation

Details Spin-on-glass planarization process with ion implantation Spin-on-glass planarization process with ion implantation

1994-04-08

1995-07-04

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437231, 437238, H01L 21316

Patent

active

054299900

ABSTRACT:
A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via A first silicon oxide layer is deposited over the metal layer. This is covered with a spin-on-glass layer. This layer is dried by baking. The spin-on-glass layer is now fully cured. The cured spin-on-glass layer is now ion implanted under the conditions of between about 1E15 to 1E17 atoms/cm.sup.2 and energy between about 50 to 100 KeV. A silicon oxide layer is deposited thereover. Via openings are now made through the silicon oxide layers and the spin-on-glass layer and filled with metal. This results in excellent planarity with no poisoned via problems. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size and can be processed without the use of an etch-back process for the cured spin on and glass layer.

REFERENCES:
patent: 4676867 (1987-06-01), Elkins et al.
patent: 4775550 (1988-10-01), Chu et al.
patent: 4885262 (1989-12-01), Ting et al.
patent: 5003062 (1991-03-01), Yen
patent: 5192697 (1993-03-01), Leong
Moriya, Modification Effects in Ion-Implanted SiO.sub.2 Spin-on-glass, J. Electrochem., Soc., vol. 140, No. 5, May 1993, pp. 1442-1449.

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