Spike-free clock switching

Details Spike-free clock switching Spike-free clock switching

2001-03-28

2002-06-25

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

Having selection between plural continuous waveforms

C327S298000

Reexamination Certificate

active

06411134

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a circuit for spike-free clock switching between clock signals which, as a digital circuit, can be fully implemented in an integrated circuit and which allows any desired phase angle of the clock signals.
In switching systems in which clock signals are duplicated for reasons of redundancy, the intention is to switch between the two clock signals of the same frequency and of any desired different phase angle without spikes/glitches occurring in the process.
This problem is conventionally solved by circuits which have a combination of monostable multivibrators with discrete components, such as resistors and capacitors for example. In these circuits, it becomes disadvantageously apparent that they cannot be fully implemented in an integrated circuit. The abovementioned objective also can be achieved via purely digital, fully integrable circuits, but they do not allow any desired phase angle of the clock signals.
The present invention is, therefore, directed to a circuit arrangement for switching between clock signals which, as a digital circuit, can be fully implemented in an integrated circuit and which allows any desired phase angle of the clock signals.
SUMMARY OF THE INVENTION
Accordingly, the inventive circuit for switching from a first clock signal to a second clock signal according to a clock select signal includes: a first circuit branch for a first clock signal, the first circuit branch having a first flip-flop, a second flip-flop, a third flip-flop, a first AND gate and a second AND gate, an output of the first flip-flop being connected to a data input of the second flip-flop, an output of the second flip-flop being connected to a second input of the first AND gate, an output of the first AND gate being connected to a data input of the third flip-flop, and an output of the third flip-flop being connected to a second input of the second AND gate, wherein an inversion of the clock select signal is fed as a select signal for the first clock signal to a data input of the fist flip-flop and to a first input of the first AND gate, wherein the first clock signal is fed to a clock input of the first flip-flop, a clock input of the second flip-flop, an inverting clock input of the third flip-flop and a first input of a second AND gate, and wherein an alarm signal associated with the first clock signal is applied to a reset input of the third flip-flop: a second circuit branch for a second clock signal, the second circuit branch having a fourth flip-flop, a fifth flip-flop, a sixth flip-flop, a third AND gate and a fourth AND gate, an output of the fourth flip-flop being connected to a data input of the fifth flip-flop, an output of the fifth flip-flop being connected to a second input of the third AND gate, an output of the third AND gate being connected to a data input of the sixth flip-flop, and an output of the sixth flip-flop being connected to a second input of the fourth AND gate, wherein the clock select signal is fed as a select signal for the second clock signal to a data input of the fourth flip-flop and to a first input of the third AND gate, wherein the second clock signal is fed to a clock input of the fourth flip-flop, a clock input of the fifth flip-flop, an inverting clock input of the sixth flip-flop, and a first input of the fourth AND gate, and wherein an alarm signal associated with a second clock signal is applied to a reset input of the sixth flip-flop; and a combination element having a first input connected to an output of the second AND gate, a second input connected to an output of the fourth AND gate, and an output connected to an output clock signal.
Accordingly, the circuit of the present invention is purely digital and requires no discrete components at all. Thus, it can be implemented in an integrated circuit such as, for example, an ASIC (Application Specific Integrated Circuit) or an FPGA (Flash Programmable Gate Array). An asynchronous signal for switching between the clock signals can be applied to the circuit arrangement. The clock signals have any desired phase angle.
Additional features and advantages of the present invention are described in, and will be apparent from, the following Detailed Description of the Invention and the Figures.


REFERENCES:
patent: 4855615 (1989-08-01), Humpleman
patent: 4970405 (1990-11-01), Hagiwara
patent: 5099141 (1992-03-01), Utsunomiya
patent: 5155380 (1992-10-01), Hwang et al.
patent: 5652536 (1997-07-01), Nookala et al.
patent: 5926044 (1999-07-01), Niimura
patent: 5969558 (1999-10-01), Abe
patent: 6107841 (2000-08-01), Goodnow
patent: 1-150921 (1989-06-01), None
patent: 10-124167 (1998-05-01), None
Patent Abstracts of Japan—10124167—May 5, 1998.
Patent Abstracts of Japan—01150921—Jun. 13, 1989.
IbM Technical Disclosure Bulletin, vol. 32, No. 98, Feb. 1990.

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