Speedy shift apparatus for use in arithmetic unit

Details Speedy shift apparatus for use in arithmetic unit Speedy shift apparatus for use in arithmetic unit

1998-05-22

2001-09-11

Ngo, Chuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S205000

Reexamination Certificate

active

06289366

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an arithmetic unit of a processor; and, more particularly, to a shift apparatus, for use in an arithmetic unit, which is capable of providing a speedy shift operation in an effective manner.
DESCRIPTION OF THE PRIOR ART
An arithmetic unit such as a floating point unit is generally employed various applications such as a processor, which contains circuits that perform arithmetic operations. The circuits are necessarily provided with a shifting apparatus for displacing or shifting an ordered set of digits one or more places to left or right, wherein the shift may be equivalent to multiplying by a power of the base.
The shifting apparatuses generally perform a shift operation based on a control signal representing a desired shift condition. However, since, in this case, the shift operations are sequentially executed in response to the control signal, it may allow the shifting apparatus to suffer uncontrollable shifting delays caused by inherent circuit delay factors. Furthermore, the additional delay time is required for the shifting apparatus to response to the control signal representing the desired shift condition. Therefore, it is difficult to implement a speedy shift apparatus to be applicable to a high speed process system.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide an apparatus, for use in an arithmetic unit, which is capable of effectively providing speedy shift operations of ordered digital data in a more efficient use of the hardware logic circuit.
In accordance with one aspect of the present invention, there is provided An apparatus, for use in an arithmetic unit, for shifting m-bit input data to left or in right, m being a positive integer, which comprises: latch means for temporarily storing the m-bit input data and additional 2n-bit, wherein n is a positive integer; shift means, receiving (m+2n)-bit data from the latch means, for providing (2n+
1
) number of m-bit shifted data; selection signal generation means for generating a selection signal based on a predetermined shift condition; and selection means, in response to the selection signal, for selecting one of the (2n+
1
) number of m-bit shifted data as an output signal of the apparatus.


REFERENCES:
patent: 5424967 (1995-06-01), Lee
patent: 5450607 (1995-09-01), Kowalczyk et al.
patent: 5559730 (1996-09-01), Marui et al.
patent: 5726926 (1998-03-01), Makino
patent: 5987603 (1999-11-01), Shah
patent: 3-113635 (1991-05-01), None
patent: 4-160533 (1992-06-01), None

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