Speed-up technique for a constant di/dt buffer

Details Speed-up technique for a constant di/dt buffer Speed-up technique for a constant di/dt buffer

1990-06-11

1991-11-19

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307263, 307542, H03K 1716

Patent

active

050668722

ABSTRACT:
The disclosure relates to a circuit and method of reducing inductive voltage spikes caused by an abrupt change in current by an output transistor, by providing an input node for receiving an input voltage signal, providing an output node, providing a first transistor coupled to the output node, receiving a predetermined voltage at the input node, controlling voltage control circuitry coupled between the input node and the first transistor and responsive to the predetermined voltage at the input node to control the voltage driving the first transistor with respect to time to provide a constant rate of change of current with respect to time in the first transistor and providing a second transistor coupled to the output node in parallel with the first transistor which turns on prior to the first transistor.

REFERENCES:
patent: 4820942 (1989-04-01), Chan
patent: 4823029 (1989-04-01), Gabara
patent: 4959561 (1990-09-01), McDermott et al.
patent: 4972101 (1990-11-01), Panotori et al.
patent: 4975598 (1990-12-01), Borkar
patent: 4987324 (1991-01-01), Wong et al.
patent: 4992677 (1991-02-01), Ishibashi et al.
patent: 5003205 (1991-03-01), Kohda et al.
patent: 5008568 (1991-04-01), Leung et al.
patent: 5010256 (1991-04-01), Dicke
patent: 5013940 (1991-05-01), Ansel

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