Speed regulation of D.C. motor using counter

Details Speed regulation of D.C. motor using counter Speed regulation of D.C. motor using counter

1978-05-10

1980-08-05

Smith, Jr., David

Electricity: motive power systems

Braking

Automatic and/or with time-delay means

318314, 318341, H02P 516

Patent

active

042164184

ABSTRACT:
A semiconductor switch connected in the motor current path is controlled by a clocked flip-flop having a switch-ON and a switch-OFF state, capable of changing states only in response to a clock pulse. RPM is selected by establishing the initial count on a downwards counter having a carryover output at which a carryover signal appears when zero count is reached. A first higher-frequency pulse train is counted by the counter. A second lower-frequency train of set pulses has a repetition frequency dependent upon motor speed. The leading end of each set pulse starts the counter counting. An unclocked flip-flop responds to the carryover signal by assuming a motor-speed-too-low state. The clocked flip-flop when clocked responds to the state of the unclocked flip-flop. The trailing flank of the set pulse clocks the clocked flip-flop so that the latter can respond to the state of the unclocked flip-flop and slightly thereafter sets the unclocked flip-flop to the motor-speed-too-high state. Thus, at the time when the clocked flip-flop responds to state of the unclocked flip-flop, the latter is in the speed-too-low state only if the carryover signal was produced before the trailing end of the set pulse.

REFERENCES:
patent: 3110853 (1963-11-01), Jones
patent: 3295039 (1966-12-01), MacDonald et al.
patent: 3724720 (1973-04-01), Bullivant
patent: 3843914 (1974-10-01), Carlson et al.
patent: 3974428 (1976-08-01), Hafle
patent: 4054820 (1977-10-01), Foster

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