Speed optimized encoder with running disparity constraint

Details Speed optimized encoder with running disparity constraint Speed optimized encoder with running disparity constraint

2006-06-20

2006-06-20

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

C341S055000

Reexamination Certificate

active

07064683

ABSTRACT:
An encoder apparatus is provided, which includes an upper encoder and first and second lower encoders. The upper encoder has an upper encoded output and a corresponding upper running disparity. The first and second lower encoders have respective first and second lower encoded outputs. The first lower encoder generates the first lower encoded output assuming the upper running disparity has a first state. The second lower encoder generates the second lower encoded output assuming the upper running disparity has a second, different state. A multiplexer multiplexes the first and second lower encoded outputs based on the upper running disparity.

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patent: 6016330 (2000-01-01), Ashley et al.
patent: 6198413 (2001-03-01), Widmer
patent: 6295010 (2001-09-01), Thiesfeld

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