Speed of execution of a conditional subtract instruction and...

Details Speed of execution of a conditional subtract instruction and... Speed of execution of a conditional subtract instruction and...

2007-06-26

2007-06-26

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10202151

ABSTRACT:
A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of dividend and the divisor, while performing a conditional subtraction instruction. The shifted divisor can conveniently replace the dividend as required for the instruction. The approach can be used to implement, among others, 2N-bit/N-bit (denoted 2N/N) division using an N-bit ALU, N/N division using N-bit ALU. The division can be implemented for all possible values of N without requiring substantially more complexity in the implementation.

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